From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 29 Apr 2018 14:46:31 +0000 (+0100)
Subject: add mvendor/march WARL update
X-Git-Tag: convert-csv-opcode-to-binary~5428
X-Git-Url: https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff_plain;h=817cd96f9d0be5a13c29e3ab42a5621ba242e8d1

add mvendor/march WARL update
---

diff --git a/isa_conflict_resolution.mdwn b/isa_conflict_resolution.mdwn
index baa2f8371..2eaee6470 100644
--- a/isa_conflict_resolution.mdwn
+++ b/isa_conflict_resolution.mdwn
@@ -267,7 +267,7 @@ turn the custom instruction into an actual binary-encoding (plus
 binary-encoding of the context-switching information).  (**TBD, Jacob,
 separate page?  review this para?**)
 
-# mvendorid/marchid WARL <a name="#mvendor_marchid_warl" />
+# mvendorid/marchid WARL <a name="#mvendor_marchid_warl"></a>
 
 (Summary: the only idea that meets the full requirements.  Needs
  toolchain backup, but only when the first chip is released)
@@ -358,7 +358,7 @@ Update 29apr2018:
   hardware-level ISA support to not be permitted to receive RISC-V
   Certification Compliance.
 
-# ioctl-like <a name="#ioctl-like" />
+# ioctl-like <a name="#ioctl-like"></a>
 
 (Summary: good solid orthogonal idea.  See [[ioctl]] for full details)