From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 25 Sep 2020 12:21:48 +0000 (+0100)
Subject: update UART page
X-Git-Tag: convert-csv-opcode-to-binary~2118
X-Git-Url: https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff_plain;h=92cde4955a5c3252a67a23ceeeef7c460196262c

update UART page
---

diff --git a/shakti/m_class/UART.mdwn b/shakti/m_class/UART.mdwn
index f4db6db74..f54f01287 100644
--- a/shakti/m_class/UART.mdwn
+++ b/shakti/m_class/UART.mdwn
@@ -1,3 +1,8 @@
-# UART RTL
+# UART 16550
 
+Several pages on opencores, including:
+
+* <https://opencores.org/projects/uart16550> which has wishbone
+* <https://github.com/freecores/uart16550> freecores version (basically same as above)
 * <https://git.m-labs.hk/M-Labs/HeavyX/src/branch/master/heavycomps/heavycomps/uart.py>
+