From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 9 Apr 2019 09:29:41 +0000 (+0100)
Subject: add link to kestrel nmigen cpu
X-Git-Tag: convert-csv-opcode-to-binary~4710
X-Git-Url: https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff_plain;h=accf72ba93cb78b88c4f0f0e4463d96ab7fadddf

add link to kestrel nmigen cpu
---

diff --git a/3d_gpu.mdwn b/3d_gpu.mdwn
index 6476468f1..45282f87b 100644
--- a/3d_gpu.mdwn
+++ b/3d_gpu.mdwn
@@ -60,3 +60,4 @@ Progress:
 * <https://chisel.eecs.berkeley.edu/api/latest/chisel3/util/DecoupledIO.html>
 * <http://www.clifford.at/papers/2016/yosys-synth-formal/slides.pdf>
 * <http://blog.lambdaconcept.com/doku.php?id=migen:tutorial>
+* <http://chiselapp.com/user/kc5tja/repository/kestrel-3/dir?ci=6c559135a301f321&name=cores/cpu>
diff --git a/shakti/m_class/EINT.mdwn b/shakti/m_class/EINT.mdwn
index 652c2c1a4..054cfb099 100644
--- a/shakti/m_class/EINT.mdwn
+++ b/shakti/m_class/EINT.mdwn
@@ -10,3 +10,4 @@ aka "PLIC"
 * <https://bitbucket.org/casl/c-class/src/0e77398a030bfd705930d0f1b8b9b5050d76e265/src/peripherals/plic/?at=master>
 * <https://github.com/RoaLogic/plic>
 * <https://github.com/pulp-platform/ariane/tree/master/src/plic>
+* <https://github.com/lowRISC/rv_plic>