From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 27 Jun 2018 17:14:27 +0000 (+0100)
Subject: correction
X-Git-Tag: convert-csv-opcode-to-binary~5098
X-Git-Url: https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff_plain;h=fe095ace2d0f82e9405e2699eb106d3b53e5de0c

correction
---

diff --git a/shakti/m_class/libre_3d_gpu.mdwn b/shakti/m_class/libre_3d_gpu.mdwn
index 661991163..4c0013820 100644
--- a/shakti/m_class/libre_3d_gpu.mdwn
+++ b/shakti/m_class/libre_3d_gpu.mdwn
@@ -81,7 +81,7 @@ modifying llvm for RISC-V to do the heavy-lifting instead.
 Then it just becomes a matter of adding vector / SIMD / parallelisation
 extensions to RISC-V, and adding support in LLVM for the same:
 
->https://lists.llvm.org/pipermail/llvm-dev/2018-April/122517.html>
+<https://lists.llvm.org/pipermail/llvm-dev/2018-April/122517.html>
 
 So if considering to base the design on RISC-V, that means turning RISC-V
 into a vector processor. Now, whilst Hwacha has been located (finally),