From 373074c7e8294e582e14ecbf625d020ad4a6a555 Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 27 Jun 2018 18:17:58 +0100 Subject: [PATCH] --- shakti/m_class/libre_3d_gpu.mdwn | 1 + 1 file changed, 1 insertion(+) diff --git a/shakti/m_class/libre_3d_gpu.mdwn b/shakti/m_class/libre_3d_gpu.mdwn index 91c9a7fe5..661991163 100644 --- a/shakti/m_class/libre_3d_gpu.mdwn +++ b/shakti/m_class/libre_3d_gpu.mdwn @@ -81,6 +81,7 @@ modifying llvm for RISC-V to do the heavy-lifting instead. Then it just becomes a matter of adding vector / SIMD / parallelisation extensions to RISC-V, and adding support in LLVM for the same: +>https://lists.llvm.org/pipermail/llvm-dev/2018-April/122517.html> So if considering to base the design on RISC-V, that means turning RISC-V into a vector processor. Now, whilst Hwacha has been located (finally), -- 2.30.2