From 64183070441d2103da6bd71c9a43b6a2812ac10d Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Thu, 18 Aug 2022 10:00:21 +0100
Subject: [PATCH]

---
 shakti/m_class/DDR.mdwn | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/shakti/m_class/DDR.mdwn b/shakti/m_class/DDR.mdwn
index 84fd205f6..d1d210806 100644
--- a/shakti/m_class/DDR.mdwn
+++ b/shakti/m_class/DDR.mdwn
@@ -4,4 +4,6 @@
 * <https://www.ohwr.org/projects/ddr3-sp6-core/wiki/wiki> - CERN DDR3 ctrl
 * <https://www.linkedin.com/in/michael-taylor-32212816/> working on DDR3 IO Cells
 * <https://github.com/waviousllc/wav-lpddr-hw>
+* <https://github.com/ZiyangYE/General-Slow-DDR3-Interface>
+* <https://github.com/ultraembedded/core_ddr3_controller>
 
-- 
2.30.2