From b3aeb1246dc24c9e54f46ed957eddebd1767102f Mon Sep 17 00:00:00 2001 From: Andrey Miroshnikov Date: Tue, 9 Jan 2024 17:33:20 +0000 Subject: [PATCH] sync_up: Update Jacob/Sadoon section --- meetings/sync_up/sync_up_2024-01-09.mdwn | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/meetings/sync_up/sync_up_2024-01-09.mdwn b/meetings/sync_up/sync_up_2024-01-09.mdwn index 3f549f939..002a4f33f 100644 --- a/meetings/sync_up/sync_up_2024-01-09.mdwn +++ b/meetings/sync_up/sync_up_2024-01-09.mdwn @@ -52,6 +52,21 @@ extra-parenthesis-in-a-wrong-spot bug for dmitry and fixed a bug luke left, but didn't actually make any coding progress beyond that. +During call, walked with Sadoon through assembler: + +``` +summary: discussing how to best split into sub-word chunks +for poly1305 +> tbh dsrd isn't better than other shifts here +It did help with taking the shift remainders and stitching them together which shortened the code quite a bit +Also considering doing sv.dsrd instead of two dsrd's since we already use setvl=2 here +> sv.dsrd is 8 bytes, just like 2x dsrd +But it's a good demo of setvl anyways +> yeah, being a good demo doesn't mean there isn't a better demo +The better demo is the mul/adds 😃 +> try using a different register than r0, the simulator may be treating that like (RA|0) and just using r0 in both iterations... +``` + # Sadoon * Working through Poly1305 assembler. -- 2.30.2