From c4bc6a269b1a7ff8a437de9fe6799ce51adf76f4 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 30 Sep 2019 11:42:59 +0100
Subject: [PATCH] add links, add bitmanip logic ops

---
 3d_gpu.mdwn                                   |  3 ++
 .../specification/bitmanip.mdwn               | 32 +++++++++++++++++++
 2 files changed, 35 insertions(+)

diff --git a/3d_gpu.mdwn b/3d_gpu.mdwn
index 41191640c..a08f9967b 100644
--- a/3d_gpu.mdwn
+++ b/3d_gpu.mdwn
@@ -81,6 +81,9 @@ Progress:
 * <https://slashdot.org/submission/9750302/nlnet-funds-development-of-a-libre-risc-v-3d-cpu>
 * <https://hardware.slashdot.org/story/19/06/02/0153243/nlnet-funds-development-of-a-libre-risc-v-3d-cpu>
 * <https://www.phoronix.com/forums/forum/hardware/graphics-cards/1104124-libre-risc-v-snags-50k-eur-grant-to-work-on-its-risc-v-3d-gpu-chip/page6>
+* <https://news.ycombinator.com/item?id=21112341>
+* <https://www.reddit.com/r/RISCV/comments/db04j3/libreriscv_3d_cpugpu_seeks_grants_for_ambitious/>
+* <https://hardware.slashdot.org/story/19/09/29/1845252/libre-risc-v-3d-cpugpu-seeks-grants-for-ambitious-expansion>
 
 # Information Resources and Tutorials
 
diff --git a/simple_v_extension/specification/bitmanip.mdwn b/simple_v_extension/specification/bitmanip.mdwn
index 6b78aa198..bc52fb763 100644
--- a/simple_v_extension/specification/bitmanip.mdwn
+++ b/simple_v_extension/specification/bitmanip.mdwn
@@ -22,6 +22,38 @@ adequate.  Some exceptions however present themselves from RVV.
 
 ## logical bit-wise instructions
 
+These are the available bitwise instructions in RVV:
+
+    vmand.mm vd, vs2, vs1     # vd[i] =   vs2[i].LSB &&  vs1[i].LSB
+    vmnand.mm vd, vs2, vs1    # vd[i] = !(vs2[i].LSB &&  vs1[i].LSB)
+    vmandnot.mm vd, vs2, vs1  # vd[i] =   vs2[i].LSB && !vs1[i].LSB
+    vmxor.mm  vd, vs2, vs1    # vd[i] =   vs2[i].LSB ^^  vs1[i].LSB
+    vmor.mm  vd, vs2, vs1     # vd[i] =   vs2[i].LSB ||  vs1[i].LSB
+    vmnor.mm  vd, vs2, vs1    # vd[i] = !(vs2[i[.LSB ||  vs1[i].LSB)
+    vmornot.mm  vd, vs2, vs1  # vd[i] =   vs2[i].LSB || !vs1[i].LSB
+    vmxnor.mm vd, vs2, vs1    # vd[i] = !(vs2[i].LSB ^^  vs1[i].LSB)
+
+The ones that exist in scalar RISC-V are:
+
+    AND rd, rs1, rs2          # rd = rs1 & rs2
+    OR  rd, rs1, rs2          # rd = rs1 | rs2
+    XOR rd, rs1, rs2          # rd = rs1 ^ rs2
+
+The ones in Bitmanip are:
+
+    ANDN rd, rs1, rs2         # rd = rs1 & ~rs2
+    ORN  rd, rs1, rs2         # rd = rs1 | ~rs2
+    XORN rd, rs1, rs2         # rd = rs1 ^ ~rs2
+
+This leaves:
+
+    NOR
+    NAND
+
+These are currently listed as "pseudo-ops" in BitManip-Draft (0.91)
+They need to be actual opcodes.
+
+
 TODO: there is an extensive table in RVV of bit-level operations:
 
 output  instruction     pseudoinstruction
-- 
2.30.2