From e191d4c9754e091c47bc85ffefb42efad4bcaa77 Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 4 Oct 2019 16:26:13 +0100 Subject: [PATCH] --- 3d_gpu.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3d_gpu.mdwn b/3d_gpu.mdwn index 669cc99d3..cc12b5a52 100644 --- a/3d_gpu.mdwn +++ b/3d_gpu.mdwn @@ -27,7 +27,7 @@ the cost of product development when it comes to PCB design and layout: We can look at larger higher-power ASICs either later or, if funding is made available, immediately. -Recent applications (Oct 2019) are for a test chip in 180nm, 64 bit, single core dual issue, around 300 to 350mhz. This will provide the confidence to go to higher geometries, as well as be a commercially viable embedded product in its own right. +Recent applications to NLNet (Oct 2019) are for a test chip in 180nm, 64 bit, single core dual issue, around 300 to 350mhz. This will provide the confidence to go to higher geometries, as well as be a commercially viable embedded product in its own right. See: -- 2.30.2