From fd752349b089c12b6ee4a3e3edf556814a1bff6f Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 26 Sep 2020 22:07:54 +0100 Subject: [PATCH] --- 3d_gpu.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3d_gpu.mdwn b/3d_gpu.mdwn index d9dff3a25..3a7d58962 100644 --- a/3d_gpu.mdwn +++ b/3d_gpu.mdwn @@ -45,7 +45,7 @@ See [[3d_gpu/articles]] online. # Progress: -* Sep 2020: [first boot](https://youtu.be/72QmWro9BSE) of Litex BIOS on a Versa ECP5 at 55mhz. DDR3 RAM initialisation successful. 180nm ASIC pinouts started. +* Sep 2020: [first boot](https://youtu.be/72QmWro9BSE) of Litex BIOS on a Versa ECP5 at 55mhz. DDR3 RAM initialisation successful. 180nm ASIC pinouts started [[180nm_Oct2020/ls180]] * Aug 2020: [first boot](https://libre-soc.org/3d_gpu/libresoc_litex_bios_first_execution_2020-08-06_16-15.png) of litex BIOS in verilator simulation * Jul 2020: first ppc64le "hello world" binary executed. 80,000 gate coriolis2 auto-layout completed with 99.98% routing. Wishbone MoU signed making available access to an additional EUR 50,000 donations from NLNet. XDC2020 and OpenPOWER conference submissions entered. * Jun 2020: core unit tests and pipeline formal correctness proofs in place. -- 2.30.2