From fe095ace2d0f82e9405e2699eb106d3b53e5de0c Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 27 Jun 2018 18:14:27 +0100 Subject: [PATCH] correction --- shakti/m_class/libre_3d_gpu.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/shakti/m_class/libre_3d_gpu.mdwn b/shakti/m_class/libre_3d_gpu.mdwn index 661991163..4c0013820 100644 --- a/shakti/m_class/libre_3d_gpu.mdwn +++ b/shakti/m_class/libre_3d_gpu.mdwn @@ -81,7 +81,7 @@ modifying llvm for RISC-V to do the heavy-lifting instead. Then it just becomes a matter of adding vector / SIMD / parallelisation extensions to RISC-V, and adding support in LLVM for the same: ->https://lists.llvm.org/pipermail/llvm-dev/2018-April/122517.html> + So if considering to base the design on RISC-V, that means turning RISC-V into a vector processor. Now, whilst Hwacha has been located (finally), -- 2.30.2