From fe53bc0a0ba8707216613b74d2b7a4d0b2700302 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 12 Jul 2018 12:50:09 +0100 Subject: [PATCH] add slides --- shakti/m_class/libre_riscv_chennai_2018.tex | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/shakti/m_class/libre_riscv_chennai_2018.tex b/shakti/m_class/libre_riscv_chennai_2018.tex index 500b38e82..a65a0d869 100644 --- a/shakti/m_class/libre_riscv_chennai_2018.tex +++ b/shakti/m_class/libre_riscv_chennai_2018.tex @@ -325,6 +325,26 @@ } +\frame{\frametitle{Interesting Missing Stuff [1] - Pinmux} + + \begin{itemize} + \item Pinmux: multiplexer of functions onto pins\\ + {\it DRAM Cell != DDR3/4, Mux Cell != Muxer} + \item Strategically extremely important to Commercial SoC success\\ + STMicro, Rockchip, Freescale, Samsung, {\bf EVERYONE} + \item Bizarrely, a libre-licensed multi-way Pinmux doesn't exist.\\ + {\it not on anyone's radar. at all.} + SiFive IOF not enough. + \item Verification (scenario analysis) and auto-generation of + TRM, header files, device-tree files, pretty much everything + makes sense (to any "lazy" Software Engineer...) + \item Corporations with their own pinmux unlikely to be interested. + \item http://git.libre-riscv.org/?p=pinmux.git \\ + http://hands.com/~lkcl/pinmux\_chennai\_2018.pdf + \end{itemize} +} + + \frame{\frametitle{TODO} \begin{itemize} -- 2.30.2