core/cpu: integrate Zynq as a classical CPU (Zynq7000), deprecate SoCZynq.
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Thu, 23 Jul 2020 15:40:46 +0000 (17:40 +0200)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Thu, 23 Jul 2020 15:40:46 +0000 (17:40 +0200)
commit041c7527ce1b378765c410e6d6e26e4883ee5e44
tree77b94bdfaf9ff2897feefd6beb82628a6bcb8b99
parent8bdf6941a36e6f386132fae7107bed0d85186541
core/cpu: integrate Zynq as a classical CPU (Zynq7000), deprecate SoCZynq.

This is the logical continuation of the recent change to avoid specific SoC classes.
A Zynq FPGA can be used with or without the PS7. When used without the PS7, a softcore CPU
can be used as with others FPGAs. When using the PS7, the softcore is replaced with the PS7
and connected to the SoC through one of the AXI GP interface.

An example is available on litex-boards.
litex/soc/cores/cpu/__init__.py
litex/soc/cores/cpu/zynq7000/__init__.py [new file with mode: 0644]
litex/soc/cores/cpu/zynq7000/core.py [new file with mode: 0644]
litex/soc/integration/builder.py
litex/soc/integration/soc.py
litex/soc/integration/soc_core.py
litex/soc/integration/soc_zynq.py [deleted file]