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(parent: 51a16fc) | patch
work-in-progress
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 15 Apr 2022 16:48:09 +0000 (17:48 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 15 Apr 2022 16:48:12 +0000 (17:48 +0100)
commit2b9b7be75a2b405456fedace894a47bc32ed2b14
tree5eabb8f6907093b627437c0ae8e760c35afeed29tree
parent51a16fc59b02e9902ea6d096d921091f1b190a3bcommit | diff
work-in-progress
asynchronous DRAM wishbone bridge which is optional when
dram_clk is not requested
src/ls2.py diff | blob | history