core: Move redirect and interrupt delivery logic to writeback
authorPaul Mackerras <paulus@ozlabs.org>
Wed, 23 Dec 2020 00:13:21 +0000 (11:13 +1100)
committerPaul Mackerras <paulus@ozlabs.org>
Mon, 18 Jan 2021 22:27:29 +0000 (09:27 +1100)
commit3cd3449b4b88e025ff9412f82737747b0c6d938a
tree809bf723a530562e31d51838f3f3fa1e838a935a
parent4fd8d9509c3fed511f3b17c62a4038fc0c525e67
core: Move redirect and interrupt delivery logic to writeback

This moves the logic for redirecting fetching and writing SRR0 and
SRR1 to writeback.  The aim is that ultimately units other than
execute1 can send their interrupts to writeback along with their
instruction completions, so that there can be multiple instructions
in flight without needing execute1 to keep track of the address
of each outstanding instruction.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
common.vhdl
control.vhdl
core.vhdl
execute1.vhdl
fetch1.vhdl
writeback.vhdl