Add Tercel PHY reset synchronization
[microwatt.git] / core_dram_tb.vhdl
2022-02-22 Raptor Engineering... Extend LiteDRAM VHDL wrapper to allow more than one...
2020-08-13 Michael NeulingMerge pull request #235 from paulusmack/master
2020-08-07 Michael NeulingMerge pull request #229 from ozbenh/litedram
2020-07-08 Benjamin Herrenschmidtlitedram: l2: Add support for more geometries
2020-06-30 Paul MackerrasMerge pull request #206 from Jbalkind/icachecleanup
2020-06-19 Michael NeulingMerge pull request #208 from paulusmack/faster
2020-06-17 Paul MackerrasMerge pull request #207 from ozbenh/misc
2020-06-14 Benjamin Herrenschmidtsoc: Rename wb_dram_ctrl to wb_ext_io and rework decoding
2020-06-13 Benjamin Herrenschmidtsoc: Add defaults for some input signals
2020-06-13 Benjamin Herrenschmidtsoc: Remove unused RESET_LOW generic
2020-06-13 Paul MackerrasMerge pull request #204 from ozbenh/spi
2020-06-13 Benjamin Herrenschmidtspi: Add simulation support
2020-06-10 Paul MackerrasMerge pull request #194 from ozbenh/misc
2020-06-10 Benjamin Herrenschmidtlitedram: Remove remnants of riscv-inits
2020-06-05 Paul MackerrasMerge pull request #191 from ozbenh/litedram
2020-06-05 Benjamin Herrenschmidtlitedram: Add support for booting without BRAM
2020-06-05 Benjamin Herrenschmidtlitedram: Add simulation support