Add Tercel PHY reset synchronization
[microwatt.git] / core_tb.vhdl
2020-06-30 Paul MackerrasMerge pull request #206 from Jbalkind/icachecleanup
2020-06-19 Michael NeulingMerge pull request #208 from paulusmack/faster
2020-06-17 Paul MackerrasMerge pull request #207 from ozbenh/misc
2020-06-13 Benjamin Herrenschmidtsoc: Don't require dram wishbones signals to be wired...
2020-06-13 Benjamin Herrenschmidtsoc: Add defaults for some input signals
2020-06-13 Benjamin Herrenschmidtsoc: Remove unused RESET_LOW generic
2020-06-13 Paul MackerrasMerge pull request #204 from ozbenh/spi
2020-06-12 Benjamin Herrenschmidtspi: Add SPI Flash controller
2020-06-05 Paul MackerrasMerge pull request #183 from shawnanastasio/addpcis
2020-06-03 Paul MackerrasMerge pull request #168 from shenki/flash-arty
2020-06-02 Anton BlanchardMerge pull request #178 from antonblanchard/intercon
2020-05-25 Benjamin Herrenschmidtsoc: Rework interconnect
2020-05-14 Paul MackerrasMerge branch 'mmu'
2020-05-14 Anton BlanchardMerge pull request #170 from antonblanchard/litedram
2020-05-08 Benjamin Herrenschmidtsyscon: Add syscon registers
2020-05-08 Benjamin Herrenschmidtsoc: Add DRAM address decoding
2020-05-08 Benjamin Herrenschmidtcore: Add alternate reset address
2020-01-21 Anton BlanchardMerge pull request #134 from paulusmack/master
2020-01-19 Anton BlanchardMerge pull request #139 from antonblanchard/reduce-mem
2020-01-19 Anton BlanchardReduce simulated and default FPGA RAM to 384kB
2019-11-15 Anton BlanchardMerge pull request #118 from antonblanchard/bus-pipeline
2019-10-30 Benjamin Herrenschmidtram: Rework main RAM interface
2019-09-24 Anton BlanchardMerge branch 'divider' of https://github.com/paulusmack...
2019-09-24 Anton BlanchardMerge pull request #69 from antonblanchard/debug-module
2019-09-20 Benjamin HerrenschmidtAdd core debug module
2019-09-12 Anton BlanchardMerge pull request #49 from antonblanchard/icache-2
2019-09-12 Anton BlanchardAdd a simple direct mapped icache
2019-09-10 Benjamin HerrenschmidtShare soc.vhdl between FPGA and sim
2019-09-10 Benjamin HerrenschmidtMove wishbone arbiter out of the core
2019-09-09 Anton BlanchardMerge pull request #33 from antonblanchard/cr-fix
2019-09-09 Anton BlanchardMerge pull request #32 from antonblanchard/register...
2019-09-09 Benjamin HerrenschmidtUse simulated UART in core test bench
2019-08-28 Anton BlanchardMerge pull request #5 from antonblanchard/travis-test
2019-08-27 Anton Blanchardmicropython only requires 512kB of BRAM
2019-08-22 Anton BlanchardInitial import of microwatt