Add Tercel PHY reset synchronization
[microwatt.git] / microwatt.core
2021-02-08 Michael NeulingMerge pull request #269 from paulusmack/pipeline
2021-02-08 Michael NeulingMerge pull request #268 from paulusmack/btc
2021-01-18 Paul Mackerrascore: Track CR hazards and bypasses using tags
2021-01-18 Paul Mackerrascore: Track GPR hazards using tags that propagate throu...
2021-01-18 Paul Mackerrasfetch1: Implement a simple branch target cache
2020-09-17 Michael NeulingMerge pull request #245 from paulusmack/fpu
2020-09-03 Paul Mackerrascore: Add framework for an FPU
2020-09-03 Paul Mackerrascore: Add support for floating-point loads and stores
2020-08-13 Michael NeulingMerge pull request #235 from paulusmack/master
2020-08-13 Michael NeulingMerge pull request #236 from ozbenh/targets
2020-08-07 Boris Shingarovfpga: Add support for Genesys2
2020-08-07 Benjamin Herrenschmidtacorn: Add support for the Acorn CLE 215+
2020-08-06 Paul MackerrasAdd random number generator and implement the darn...
2020-07-09 Michael NeulingMerge pull request #228 from ozbenh/misc
2020-07-08 Benjamin Herrenschmidtcorefile/nexys_video: Parameter fixes
2020-06-30 Paul MackerrasMerge pull request #206 from Jbalkind/icachecleanup
2020-06-29 Michael NeulingMerge pull request #213 from ozbenh/uart16550
2020-06-29 Michael NeulingMerge pull request #212 from ozbenh/liteeth
2020-06-25 Benjamin Herrenschmidtuart: Make 16550 the default
2020-06-23 Benjamin Herrenschmidtuart: Import and hook up opencore 16550 compatible...
2020-06-23 Benjamin Herrenschmidtliteeth: Hook up LiteX LiteEth ethernet controller
2020-06-19 Michael NeulingMerge pull request #208 from paulusmack/faster
2020-06-16 Paul Mackerrasfpga: Add a xilinx_specific fileset to microwatt.core
2020-06-16 Paul MackerrasMake LOG_LENGTH configurable per FPGA variant
2020-06-13 Paul Mackerrasmultiply: Use DSP48 slices for multiplication on Xilinx...
2020-06-13 Paul Mackerrascore: Remove fetch2 pipeline stage
2020-06-13 Paul MackerrasMerge pull request #204 from ozbenh/spi
2020-06-12 Benjamin Herrenschmidtspi: Add SPI Flash controller
2020-06-05 Paul MackerrasMerge pull request #191 from ozbenh/litedram
2020-06-05 Benjamin Herrenschmidtlitedram: Add an L2 cache with store queue
2020-06-05 Benjamin Herrenschmidtlitedram: Add support for booting without BRAM
2020-06-03 Paul MackerrasMerge pull request #168 from shenki/flash-arty
2020-05-19 Anton BlanchardMerge branch 'master' into litedram
2020-05-19 Anton BlanchardMerge pull request #176 from antonblanchard/console...
2020-05-19 Anton BlanchardMerge pull request #174 from antonblanchard/yosys-fixes
2020-05-18 Anton BlanchardMerge pull request #169 from paulusmack/mmu
2020-05-14 Paul MackerrasMerge branch 'mmu'
2020-05-14 Anton BlanchardMerge pull request #170 from antonblanchard/litedram
2020-05-08 Benjamin Herrenschmidtsyscon: Add syscon registers
2020-05-08 Benjamin Herrenschmidtfpga: Hookup nexys-video to litedram
2020-05-08 Benjamin Herrenschmidtfpga: Hookup Arty to litedram
2020-05-08 Paul MackerrasAdd framework for implementing an MMU
2020-05-08 Benjamin Herrenschmidtlitedram: Add basic support for LiteX LiteDRAM
2020-05-08 Benjamin HerrenschmidtChange default frequency to 100Mhz
2020-05-08 Benjamin Herrenschmidtxics: Add missing fusesoc core file
2020-04-16 Anton BlanchardMerge pull request #159 from shenki/fusesoc-ram-16k
2020-04-15 Joel StanleySet default RAM to be 16K in microwatt.core
2019-11-15 Anton BlanchardMerge pull request #118 from antonblanchard/bus-pipeline
2019-10-30 Benjamin Herrenschmidtram: Rework main RAM interface
2019-10-30 Benjamin HerrenschmidtAdd option to not flatten hierarchy
2019-10-25 Anton BlanchardMerge pull request #113 from mikey/exec-sim-remove
2019-10-25 Anton BlanchardMerge pull request #114 from antonblanchard/dcache
2019-10-23 Benjamin Herrenschmidtdcache: Add a dcache
2019-10-16 Anton BlanchardMerge pull request #105 from paulusmack/writeback
2019-10-15 Paul MackerrasRemove execute2 stage
2019-10-15 Anton BlanchardMerge pull request #103 from paulusmack/divider
2019-10-15 Anton BlanchardMerge pull request #102 from antonblanchard/gpr-hazard-5-c
2019-10-15 Anton BlanchardAdd CR hazard detection
2019-10-15 Anton BlanchardMerge pull request #101 from antonblanchard/gpr-hazard-5-b
2019-10-14 Anton BlanchardAdd GPR hazard detection
2019-10-14 Anton BlanchardMerge pull request #100 from antonblanchard/gpr-hazard-5-a
2019-10-14 Anton BlanchardSeparate issue control into its own unit
2019-10-11 Anton BlanchardMerge pull request #84 from classilla/master
2019-10-11 Anton BlanchardMerge pull request #89 from mikey/gitignore
2019-10-10 Anton BlanchardMerge pull request #87 from antonblanchard/cmod-a7...
2019-10-10 Anton BlanchardFix cmod-a7 frequency
2019-10-10 Anton BlanchardMerge pull request #79 from deece/uart_address
2019-10-09 Anton BlanchardMerge pull request #83 from paulusmack/logical
2019-10-09 Anton BlanchardMerge pull request #81 from antonblanchard/logical
2019-10-09 Anton BlanchardMerge pull request #82 from antonblanchard/icache-set...
2019-10-08 Paul Mackerrasexecute: Consolidate count-leading/trailing-zeroes...
2019-10-08 Anton BlanchardConsolidate logical instructions
2019-10-08 Benjamin Herrenschmidticache: Set associative icache
2019-10-08 Benjamin Herrenschmidtplru: Add a simple PLRU module
2019-10-07 Anton BlanchardMerge pull request #78 from paulusmack/new-decode
2019-10-07 Paul MackerrasAdd a rotate/mask/shift unit and use it in execute1
2019-09-30 Anton BlanchardMerge pull request #77 from antonblanchard/timing
2019-09-30 Anton BlanchardMerge pull request #76 from antonblanchard/misc
2019-09-30 Benjamin HerrenschmidtImprove PLL/MMCM clocks configuration
2019-09-30 Benjamin Herrenschmidtcorefile: Remove duplicate wishbone_debug_master
2019-09-30 Benjamin Herrenschmidtfpga: Arty A7's don't need multiple filesets
2019-09-28 Anton BlanchardMerge pull request #75 from paulusmack/master
2019-09-27 Paul Mackerrasfpga: Add definitions for Arty A7-100 board
2019-09-24 Anton BlanchardMerge branch 'divider' of https://github.com/paulusmack...
2019-09-24 Anton BlanchardMerge pull request #69 from antonblanchard/debug-module
2019-09-23 Anton BlanchardAdd core_debug.vhdl to fusesoc configs
2019-09-23 Paul MackerrasAdd a divider unit and a testbench for it
2019-09-20 Benjamin HerrenschmidtWishbone debug module
2019-09-20 Benjamin HerrenschmidtAdd a debug (DMI) bus and a JTAG interface to it on...
2019-09-12 Anton BlanchardMerge pull request #49 from antonblanchard/icache-2
2019-09-12 Anton BlanchardAdd a simple direct mapped icache
2019-09-10 Benjamin HerrenschmidtShare soc.vhdl between FPGA and sim
2019-09-10 Benjamin HerrenschmidtPass wishbone record to bram memory module
2019-09-10 Benjamin HerrenschmidtSplit FPGA toplevel from soc
2019-09-08 Anton BlanchardMerge pull request #19 from antonblanchard/cmod-a7
2019-09-08 Anton BlanchardCmod A7-35 support
2019-09-08 Anton BlanchardMerge pull request #20 from antonblanchard/reset-rework2
2019-09-07 Anton BlanchardRework SOC reset
2019-09-03 Anton BlanchardMerge pull request #16 from antonblanchard/decode2_rework2
2019-09-03 Anton BlanchardRework decode2
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