build,vendor: never carry around parts of differential signals.
authorwhitequark <whitequark@whitequark.org>
Fri, 31 Jul 2020 13:17:39 +0000 (13:17 +0000)
committerwhitequark <whitequark@whitequark.org>
Fri, 31 Jul 2020 18:41:59 +0000 (18:41 +0000)
commitd964ba9cc45490b141c8c4c4c3d8add1a26a739d
tree0883188e1648f982e3a27bf0b89c4c09dac3d3ef
parentc9662c5ff8b17988a48df499127a724bd2528490
build,vendor: never carry around parts of differential signals.

When a port component is skipped, it should appear neither in the RTL
nor in the constraint file. However, passing around components of
differential ports explicitly makes that harder.

Fixes #456.
Supersedes #457.

Co-authored-by: Jean THOMAS <git0@pub.jeanthomas.me>
nmigen/build/plat.py
nmigen/build/res.py
nmigen/test/test_build_res.py
nmigen/vendor/intel.py
nmigen/vendor/lattice_ecp5.py
nmigen/vendor/lattice_ice40.py
nmigen/vendor/lattice_machxo_2_3l.py
nmigen/vendor/xilinx_7series.py
nmigen/vendor/xilinx_spartan_3_6.py
nmigen/vendor/xilinx_ultrascale.py