speed up ==, hash, <, >, <=, and >= for plain_data

[nmutil.git] / src / nmutil / latch.py

diff --git a/src/nmutil/latch.py b/src/nmutil/latch.py
index f4c03ab9f5784f7c1365bc3c8454c12fc6e95140..e2d7541d396fa7468668f4bd903346abd504a94f 100644 (file)
--- a/src/nmutil/latch.py
+++ b/src/nmutil/latch.py
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: LGPL-3-or-later
 """
     This work is funded through NLnet under Grant 2019-02-012
 
@@ -45,7 +46,7 @@ def latchregister(m, incoming, outgoing, settrue, name=None):
     else:
         reg = Signal.like(incoming, name=name)
     m.d.comb += outgoing.eq(Mux(settrue, incoming, reg))
-    with m.If(settrue): # pass in some kind of expression/condition here
+    with m.If(settrue):  # pass in some kind of expression/condition here
         m.d.sync += reg.eq(incoming)      # latch input into register
     return reg
 
@@ -65,7 +66,7 @@ class SRLatch(Elaboratable):
         qint = mkname("qint", name)
         qlq_n = mkname("qlq", name)
         self.s = Signal(llen, name=s_n, reset=0)
-        self.r = Signal(llen, name=r_n, reset=(1<<llen)-1) # defaults to off
+        self.r = Signal(llen, name=r_n, reset=(1 << llen)-1)  # defaults to off
         self.q = Signal(llen, name=q_n, reset_less=True)
         self.qn = Signal(llen, name=qn_n, reset_less=True)
         self.qlq = Signal(llen, name=qlq_n, reset_less=True)
@@ -74,13 +75,15 @@ class SRLatch(Elaboratable):
     def elaborate(self, platform):
         m = Module()
 
-        m.d.sync += self.q_int.eq((self.q_int & ~self.r) | self.s)
+        next_o = Signal(self.llen, reset_less=True)
+        m.d.comb += next_o.eq((self.q_int & ~self.r) | self.s)
+        m.d.sync += self.q_int.eq(next_o)
         if self.sync:
             m.d.comb += self.q.eq(self.q_int)
         else:
-            m.d.comb += self.q.eq((self.q_int & ~self.r) | self.s)
+            m.d.comb += self.q.eq(next_o)
         m.d.comb += self.qn.eq(~self.q)
-        m.d.comb += self.qlq.eq(self.q | self.q_int) # useful output
+        m.d.comb += self.qlq.eq(self.q | self.q_int)  # useful output
 
         return m
 
@@ -111,6 +114,7 @@ def sr_sim(dut):
     yield
     yield
 
+
 def test_sr():
     dut = SRLatch(llen=4)
     vl = rtlil.convert(dut, ports=dut.ports())
@@ -126,5 +130,6 @@ def test_sr():
 
     run_simulation(dut, sr_sim(dut), vcd_name='test_srlatch_async.vcd')
 
+
 if __name__ == '__main__':
     test_sr()