add rst0 to sdram

[pinmux.git] / src / bsv / bsv_lib / soc_template.bsv

diff --git a/src/bsv/bsv_lib/soc_template.bsv b/src/bsv/bsv_lib/soc_template.bsv
index 0e0886ecf9ff83e416f1096212eacfce055c5fd3..cd2fcefb7066beb3d48502d4d09aba337fbe83d9 100644 (file)
--- a/src/bsv/bsv_lib/soc_template.bsv
+++ b/src/bsv/bsv_lib/soc_template.bsv
@@ -62,9 +62,6 @@ package socgen;
     `ifdef BOOTROM
         import BootRom                 ::*;
     `endif
-    `ifdef SDRAM
-        import sdr_top                  :: *;
-    `endif
     `ifdef BRAM
         import Memory_AXI4     ::*;
     `endif
@@ -83,9 +80,6 @@ package socgen;
     `ifdef VME
         import vme_master::*;
     `endif
-    `ifdef FlexBus
-        import FlexBus_Types::*;
-    `endif
 {0}
 
     /*========================= */
@@ -95,9 +89,6 @@ package socgen;
         (*always_ready,always_enabled*)
         method Action boot_sequence(Bit#(1) bootseq);
             
-        `ifdef SDRAM 
-            (*always_ready*) interface Ifc_sdram_out sdram_out; 
-        `endif
         `ifdef DDR
             (*prefix="M_AXI"*) interface
                    AXI4_Master_IFC#(`PADDR, `DATA, `USERSPACE) master;
@@ -119,7 +110,7 @@ package socgen;
     (*synthesize*)
     module mkSoc #(Bit#(`VADDR) reset_vector,
                  Clock slow_clock, Reset slow_reset, Clock uart_clock, 
-                 Reset uart_reset, Clock clk0, Clock tck, Reset trst
+                 Reset uart_reset, Clock clk0, Reset rst0, Clock tck, Reset trst
                  `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif )(Ifc_Soc);
         Clock core_clock <-exposeCurrentClock; // slow peripheral clock
         Reset core_reset <-exposeCurrentReset; // slow peripheral reset
@@ -132,9 +123,6 @@ package socgen;
         `ifdef BOOTROM
             BootRom_IFC bootrom <-mkBootRom;
         `endif
-        `ifdef SDRAM
-            Ifc_sdr_slave sdram<- mksdr_axi4_slave(clk0);
-        `endif
         `ifdef BRAM
             Memory_IFC#(`SDRAMMemBase,`Addr_space)main_memory <- 
                         mkMemory("code.mem.MSB","code.mem.LSB","MainMEM");
@@ -175,6 +163,7 @@ package socgen;
          mkConnection (dma.mmu, fabric.v_from_masters
                               [fromInteger(valueOf(DMA_master_num))]);
         `endif
+{13}
 
 
         // Connect fabric to memory slaves
@@ -183,14 +172,6 @@ package socgen;
                               [fromInteger(valueOf(Debug_slave_num))],
                               core.debug_slave);
             `endif
-            `ifdef SDRAM       
-                mkConnection (fabric.v_to_slaves 
-                              [fromInteger(valueOf(Sdram_slave_num))], 
-                              sdram.axi4_slave_sdram); // 
-            mkConnection (fabric.v_to_slaves 
-                              [fromInteger(valueOf(Sdram_cfg_slave_num))],
-                              sdram.axi4_slave_cntrl_reg); // 
-      `endif
       `ifdef BRAM
                 mkConnection(fabric.v_to_slaves
                               [fromInteger(valueOf(Sdram_slave_num))],
@@ -307,9 +288,6 @@ package socgen;
         `endif 
          method Action boot_sequence(Bit#(1) bootseq) = 
                             core.boot_sequence(bootseq);
-        `ifdef SDRAM
-            interface sdram_out=sdram.ifc_sdram_out;
-        `endif
         `ifdef DDR
           interface master=fabric.v_to_slaves
                                 [fromInteger(valueOf(Sdram_slave_num))];