(*always_ready,always_enabled*)
method Action boot_sequence(Bit#(1) bootseq);
- `ifdef SDRAM
- (*always_ready*) interface Ifc_sdram_out sdram_out;
- `endif
`ifdef DDR
(*prefix="M_AXI"*) interface
AXI4_Master_IFC#(`PADDR, `DATA, `USERSPACE) master;
(*synthesize*)
module mkSoc #(Bit#(`VADDR) reset_vector,
Clock slow_clock, Reset slow_reset, Clock uart_clock,
- Reset uart_reset, Clock clk0, Clock tck, Reset trst
+ Reset uart_reset, Clock clk0, Reset rst0, Clock tck, Reset trst
`ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif )(Ifc_Soc);
Clock core_clock <-exposeCurrentClock; // slow peripheral clock
Reset core_reset <-exposeCurrentReset; // slow peripheral reset
[fromInteger(valueOf(Debug_slave_num))],
core.debug_slave);
`endif
- `ifdef SDRAM
- mkConnection (fabric.v_to_slaves
- [fromInteger(valueOf(Sdram_slave_num))],
- sdram.axi4_slave_sdram); //
- mkConnection (fabric.v_to_slaves
- [fromInteger(valueOf(Sdram_cfg_slave_num))],
- sdram.axi4_slave_cntrl_reg); //
- `endif
`ifdef BRAM
mkConnection(fabric.v_to_slaves
[fromInteger(valueOf(Sdram_slave_num))],
`endif
method Action boot_sequence(Bit#(1) bootseq) =
core.boot_sequence(bootseq);
- `ifdef SDRAM
- interface sdram_out=sdram.ifc_sdram_out;
- `endif
`ifdef DDR
interface master=fabric.v_to_slaves
[fromInteger(valueOf(Sdram_slave_num))];