add rst0 to sdram

[pinmux.git] / src / bsv / bsv_lib / soc_template.bsv

diff --git a/src/bsv/bsv_lib/soc_template.bsv b/src/bsv/bsv_lib/soc_template.bsv
index 9d853f7f93c4a13b9a7ba6be806541939cfcf34b..cd2fcefb7066beb3d48502d4d09aba337fbe83d9 100644 (file)
--- a/src/bsv/bsv_lib/soc_template.bsv
+++ b/src/bsv/bsv_lib/soc_template.bsv
@@ -28,7 +28,7 @@ NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 -------------------------------------------------------------------
 */
-package Soc;
+package socgen;
     /*====== Package imports === */
     import FIFO::*;
     import FIFOF::*;
@@ -38,22 +38,23 @@ package Soc;
     import Vector::*;
     import Connectable::*;
     import Clocks::*;
-    /*========================== */
+
     /*=== Project imports === */
+    import ifc_sync:: *;
     import ConcatReg::*;
     import AXI4_Types::*;
     import AXI4_Fabric::*;
     import defined_types::*;
     import MemoryMap            :: *;
     import slow_peripherals::*;
+    import fast_memory_map::*;
+    import slow_memory_map::*;
+`ifdef DEBUG
     `include "defines.bsv"
+`endif
     `include "instance_defines.bsv"
+    `include "core_parameters.bsv"
 {8}
-    /*====== AXI4 slave declarations =======*/
-{3}
-    /*====== AXI4 Master declarations =======*/
-{4}
-
 
     `ifdef DMA
         import DMA                              :: *;
@@ -61,9 +62,6 @@ package Soc;
     `ifdef BOOTROM
         import BootRom                 ::*;
     `endif
-    `ifdef SDRAM
-        import sdr_top                  :: *;
-    `endif
     `ifdef BRAM
         import Memory_AXI4     ::*;
     `endif
@@ -82,23 +80,18 @@ package Soc;
     `ifdef VME
         import vme_master::*;
     `endif
-    `ifdef FlexBus
-        import FlexBus_Types::*;
-    `endif
 {0}
 
     /*========================= */
     interface Ifc_Soc;
-        interface SP_ios slow_ios;
+        interface SP_dedicated_ios slow_ios;
+        interface IOCellSide iocell_side;
         (*always_ready,always_enabled*)
         method Action boot_sequence(Bit#(1) bootseq);
             
-        `ifdef SDRAM 
-            (*always_ready*) interface Ifc_sdram_out sdram_out; 
-        `endif
-        ifdef DDR
+        `ifdef DDR
             (*prefix="M_AXI"*) interface
-                   AXI4_Master_IFC#(`PADDR, `Reg_width, `USERSPACE) master;
+                   AXI4_Master_IFC#(`PADDR, `DATA, `USERSPACE) master;
         `endif
         `ifdef HYPER
              (*always_ready,always_enabled*)   
@@ -109,16 +102,15 @@ package Soc;
              interface Vme_out  proc_ifc;
              interface Data_bus_inf proc_dbus;
         `endif
-        `ifdef FlexBus
-             interface FlexBus_Master_IFC flexbus_out;
-        `endif
 {1}
     endinterface
 
+    //============ mkSoc module =================
+
     (*synthesize*)
     module mkSoc #(Bit#(`VADDR) reset_vector,
                  Clock slow_clock, Reset slow_reset, Clock uart_clock, 
-                 Reset uart_reset, Clock clk0, Clock tck, Reset trst
+                 Reset uart_reset, Clock clk0, Reset rst0, Clock tck, Reset trst
                  `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif )(Ifc_Soc);
         Clock core_clock <-exposeCurrentClock; // slow peripheral clock
         Reset core_reset <-exposeCurrentReset; // slow peripheral reset
@@ -131,9 +123,6 @@ package Soc;
         `ifdef BOOTROM
             BootRom_IFC bootrom <-mkBootRom;
         `endif
-        `ifdef SDRAM
-            Ifc_sdr_slave sdram<- mksdr_axi4_slave(clk0);
-        `endif
         `ifdef BRAM
             Memory_IFC#(`SDRAMMemBase,`Addr_space)main_memory <- 
                         mkMemory("code.mem.MSB","code.mem.LSB","MainMEM");
@@ -147,19 +136,18 @@ package Soc;
             `ifdef VME
             Ifc_vme_top             vme             <-mkvme_top();
             `endif     
-        `ifdef FlexBus
-            AXI4_Slave_to_FlexBus_Master_Xactor_IFC #(32, 64,0)
-                            flexbus <- mkAXI4_Slave_to_FlexBus_Master_Xactor;
-        `endif
         Ifc_slow_peripherals slow_peripherals <-mkslow_peripherals(
-                          core_clock, core_reset, uart_clock, 
-                          uart_reset, clocked_by slow_clock ,
-                          reset_by slow_reset 
+                          core_clock, core_reset,
+                          uart_clock, uart_reset,
+                          clocked_by slow_clock, reset_by slow_reset
                           `ifdef PWM_AXI4Lite , ext_pwm_clock `endif );        
 
+        // clock sync mkConnections
+{12}
+
         // Fabric
-        AXI4_Fabric_IFC #(Num_Masters, Num_Slaves,
-                          `PADDR, `Reg_width,`USERSPACE)
+        AXI4_Fabric_IFC #(Num_Masters, Num_Fast_Slaves,
+                          `PADDR, `DATA,`USERSPACE)
                         fabric <- mkAXI4_Fabric(fn_addr_to_slave_num);
 
         // Connect traffic generators to fabric
@@ -175,6 +163,7 @@ package Soc;
          mkConnection (dma.mmu, fabric.v_from_masters
                               [fromInteger(valueOf(DMA_master_num))]);
         `endif
+{13}
 
 
         // Connect fabric to memory slaves
@@ -183,14 +172,6 @@ package Soc;
                               [fromInteger(valueOf(Debug_slave_num))],
                               core.debug_slave);
             `endif
-            `ifdef SDRAM       
-                mkConnection (fabric.v_to_slaves 
-                              [fromInteger(valueOf(Sdram_slave_num))], 
-                              sdram.axi4_slave_sdram); // 
-            mkConnection (fabric.v_to_slaves 
-                              [fromInteger(valueOf(Sdram_cfg_slave_num))],
-                              sdram.axi4_slave_cntrl_reg); // 
-      `endif
       `ifdef BRAM
                 mkConnection(fabric.v_to_slaves
                               [fromInteger(valueOf(Sdram_slave_num))],
@@ -219,11 +200,9 @@ package Soc;
                               [fromInteger(valueOf(VME_slave_num))],
                               vme.slave_axi_vme);
             `endif
-            `ifdef FlexBus
-                mkConnection (fabric.v_to_slaves
-                              [fromInteger(valueOf(FlexBus_slave_num))],
-                              flexbus.axi_side);
-            `endif
+
+//          pin connections
+{9}
 
             // fabric connections
 {5}
@@ -277,7 +256,7 @@ package Soc;
                                         mkSyncBitToCC(slow_clock,slow_reset);
             SyncBitIfc#(Bit#(1)) clint_msip_int <-
                                         mkSyncBitToCC(slow_clock,slow_reset);
-            Reg#(Bit#(`Reg_width)) clint_mtime_value <-
+            Reg#(Bit#(`DATA)) clint_mtime_value <-
                                         mkSyncRegToCC(0,slow_clock,slow_reset);
             rule synchronize_clint_data;
                 clint_mtip_int.send(slow_peripherals.mtip_int);
@@ -306,20 +285,16 @@ package Soc;
         `ifdef VME
             interface  proc_ifc = vme.proc_ifc;
             interface   proc_dbus = vme.proc_dbus;
-        `endif 
-        `ifdef FlexBus
-            interface flexbus_out = flexbus.flexbus_side;
         `endif 
          method Action boot_sequence(Bit#(1) bootseq) = 
                             core.boot_sequence(bootseq);
-        `ifdef SDRAM
-            interface sdram_out=sdram.ifc_sdram_out;
-        `endif
         `ifdef DDR
           interface master=fabric.v_to_slaves
                                 [fromInteger(valueOf(Sdram_slave_num))];
         `endif
-        interface slow_ios=slow_peripherals.slow_ios;
+        interface slow_ios = slow_peripherals.slow_ios;
+        interface iocell_side = slow_peripherals.iocell_side;
+
 {6}
     endmodule
 endpackage