from bsv.wire_def import generic_io # special case
from bsv.wire_def import muxwire # special case
from ifacebase import InterfacesBase
-from bsv.peripheral_gen import PFactory
-from bsv.peripheral_gen import axi_slave_declarations
-slowfactory = PFactory()
+from bsv.peripheral_gen import PeripheralIface
+from bsv.peripheral_gen import PeripheralInterfaces
class Pin(object):
"""
def __init__(self, name,
+ name_=None,
+ idx=None,
ready=True,
enabled=True,
io=False,
bitspec=None,
outenmode=False):
self.name = name
+ self.name_ = name_
+ self.idx = idx
self.ready = ready
self.enabled = enabled
self.io = io
Action io0_inputval (Bit#(1) in);
"""
+ def ifacepfmt(self, fmtfn):
+ res = ' '
+ status = []
+ res += "interface "
+ name = fmtfn(self.name_)
+ if self.action:
+ res += "Put"
+ else:
+ res += "Get"
+ res += "#(%s) %s;" % (self.bitspec, name)
+ return res
+
def ifacefmt(self, fmtfn):
res = ' '
status = []
res += ";"
return res
- # sample bsv method definition :
- """
- method Action cell0_mux(Bit#(2) in);
- wrcell0_mux<=in;
- endmethod
- """
-
def ifacedef(self, fmtoutfn, fmtinfn, fmtdecfn):
res = ' method '
if self.action:
fmtname = fmtoutfn(self.name)
res += "%s=%s;" % (self.name, fmtname)
return res
+ # sample bsv method definition :
+ """
+ method Action cell0_mux(Bit#(2) in);
+ wrcell0_mux<=in;
+ endmethod
+ """
+
# sample bsv wire (wire definiton):
"""
Wire#(Bit#(2)) wrcell0_mux<-mkDWire(0);
res += "<-mkDWire(0);"
return res
+ def ifacedef2(self, fmtoutfn, fmtinfn, fmtdecfn):
+ if self.action:
+ fmtname = fmtinfn(self.name)
+ res = " interface %s = interface Put\n" % self.name_
+ res += ' method '
+ res += "Action put"
+ #res += fmtdecfn(self.name)
+ res += '(%s in);\n' % self.bitspec
+ res += ' %s<=in;\n' % fmtname
+ res += ' endmethod\n'
+ res += ' endinterface;'
+ else:
+ fmtname = fmtoutfn(self.name)
+ res = " interface %s = interface Get\n" % self.name_
+ res += ' method ActionValue#'
+ res += '(%s) get;\n' % self.bitspec
+ res += " return %s;\n" % (fmtname)
+ res += ' endmethod\n'
+ res += ' endinterface;'
+ return res
+
+ def ifacedef3(self, idx, fmtoutfn, fmtinfn, fmtdecfn):
+ if self.action:
+ fmtname = fmtinfn(self.name)
+ if self.name.endswith('outen'):
+ name = "tputen"
+ else:
+ name = "tput"
+ res = " %s <= in[%d];" % (fmtname, idx)
+ else:
+ fmtname = fmtoutfn(self.name)
+ res = " tget[%d] = %s;" % (idx, fmtname)
+ name = 'tget'
+ return (name, res)
+
+
+class InterfaceFmt(object):
+
+ def ifacepfmtdecpin(self, pin):
+ return pin.ifacepfmt(self.ifacepfmtdecfn)
+
+ def ifacepfmtdecfn(self, name):
+ return name
+
+ def ifacefmtoutfn(self, name):
+ return "wr%s" % name # like wruart
+
+ def ifacefmtdecfn2(self, name):
+ return name # like: uart
+
+ def ifacefmtdecfn3(self, name):
+ """ HACK! """
+ return "%s_outen" % name # like uart_outen
-class Interface(object):
+ def ifacefmtinfn(self, name):
+ return "wr%s" % name
+
+ def ifacedef2pin(self, pin):
+ decfn = self.ifacefmtdecfn2
+ outfn = self.ifacefmtoutfn
+ # print pin, pin.outenmode
+ if pin.outenmode:
+ decfn = self.ifacefmtdecfn3
+ outfn = self.ifacefmtoutenfn
+ return pin.ifacedef2(outfn, self.ifacefmtinfn,
+ decfn)
+
+ def vectorifacedef2(self, pins, count, names, bitfmt, *args):
+ tput = []
+ tget = []
+ tputen = []
+ if len(pins) == 0:
+ return ''
+ # XXX HACK! assume in, out and inout, create set of indices
+ # that are repeated three times.
+ plens = []
+ # ARG even worse hack for LCD *sigh*...
+ if names[1] is None and names[2] is None:
+ plens = range(len(pins))
+ else:
+ for i in range(0, len(pins), 3):
+ plens += [i / 3, i / 3, i / 3]
+ for (typ, txt) in map(self.ifacedef3pin, plens, pins):
+ if typ == 'tput':
+ tput.append(txt)
+ elif typ == 'tget':
+ tget.append(txt)
+ elif typ == 'tputen':
+ tputen.append(txt)
+ tput = '\n'.join(tput).format(*args)
+ tget = '\n'.join(tget).format(*args)
+ tputen = '\n'.join(tputen).format(*args)
+ bitfmt = bitfmt.format(count)
+ template = ["""\
+ interface {3} = interface Put#({0})
+ method Action put({2} in);
+{1}
+ endmethod
+ endinterface;
+""",
+ """\
+ interface {3} = interface Put#({0})
+ method Action put({2} in);
+{1}
+ endmethod
+ endinterface;
+""",
+ """\
+ interface {3} = interface Get#({0})
+ method ActionValue#({2}) get;
+ {2} tget;
+{1}
+ return tget;
+ endmethod
+ endinterface;
+"""]
+ res = ''
+ tlist = [tput, tputen, tget]
+ for i, n in enumerate(names):
+ if n:
+ res += template[i].format(count, tlist[i], bitfmt, n)
+ return '\n' + res + '\n'
+
+
+class Interface(PeripheralIface, InterfaceFmt):
""" create an interface from a list of pinspecs.
each pinspec is a dictionary, see Pin class arguments
single indicates that there is only one of these, and
"""
def __init__(self, ifacename, pinspecs, ganged=None, single=False):
+ PeripheralIface.__init__(self, ifacename)
+ InterfaceFmt.__init__(self)
self.ifacename = ifacename
self.ganged = ganged or {}
self.pins = [] # a list of instances of class Pin
self.pinspecs = pinspecs # a list of dictionary
self.single = single
- self.slow = None
- slow = slowfactory.getcls(ifacename)
- if slow:
- self.slow = slow()
- for p in pinspecs:
+ for idx, p in enumerate(pinspecs):
_p = {}
_p.update(p)
if 'type' in _p:
del _p['outen']
for psuffix in ['out', 'outen', 'in']:
# changing the name (like sda) to (twi_sda_out)
+ _p['name_'] = "%s_%s" % (p['name'], psuffix)
_p['name'] = "%s_%s" % (self.pname(p['name']), psuffix)
_p['action'] = psuffix != 'in'
+ _p['idx'] = idx
self.pins.append(Pin(**_p))
# will look like {'name': 'twi_sda_out', 'action': True}
# {'name': 'twi_sda_outen', 'action': True}
#{'name': 'twi_sda_in', 'action': False}
# NOTice - outen key is removed
else:
+ name = p['name']
+ if name.isdigit(): # HACK! deals with EINT case
+ name = self.pname(name)
+ _p['name_'] = name
+ _p['idx'] = idx
_p['name'] = self.pname(p['name'])
self.pins.append(Pin(**_p))
return 'input'
return None
- def pname(self, name):
+ def iname(self):
""" generates the interface spec e.g. flexbus_ale
if there is only one flexbus interface, or
sd{0}_cmd if there are several. string format
appropriate. single mode stops the numerical extension.
"""
if self.single:
- return '%s_%s' % (self.ifacename, name)
- return '%s{0}_%s' % (self.ifacename, name)
+ return self.ifacename
+ return '%s{0}' % self.ifacename
+
+ def pname(self, name):
+ """ generates the interface spec e.g. flexbus_ale
+ if there is only one flexbus interface, or
+ sd{0}_cmd if there are several. string format
+ function turns this into sd0_cmd, sd1_cmd as
+ appropriate. single mode stops the numerical extension.
+ """
+ return "%s_%s" % (self.iname(), name)
def busfmt(self, *args):
""" this function creates a bus "ganging" system based
res += '\n'
return '\n' + res
+ def ifacepfmt(self, *args):
+ res = '\n'.join(map(self.ifacepfmtdecpin, self.pins)).format(*args)
+ return '\n' + res # pins is a list
+
def ifacefmt(self, *args):
res = '\n'.join(map(self.ifacefmtdecpin, self.pins)).format(*args)
return '\n' + res # pins is a list
def ifacefmtdecfn(self, name):
return name # like: uart
- def ifacefmtdecfn2(self, name):
- return name # like: uart
-
- def ifacefmtdecfn3(self, name):
- """ HACK! """
- return "%s_outen" % name # like uart_outen
-
- def ifacefmtoutfn(self, name):
- return "wr%s" % name # like wruart
-
- def ifacefmtinfn(self, name):
- return "wr%s" % name
-
def wirefmtpin(self, pin):
return pin.wirefmt(self.ifacefmtoutfn, self.ifacefmtinfn,
self.ifacefmtdecfn2)
res = res.format(*args)
return '\n' + res + '\n'
- def slowimport(self):
- if not self.slow:
- return ''
- return self.slow.importfn().format()
-
- def slowifdecl(self, count):
- if not self.slow:
- return ''
- return self.slow.ifacedecl().format(count, self.ifacename)
-
- def axi_reg_def(self, start, count):
- if not self.slow:
- return ('', 0)
- return self.slow.axi_reg_def(start, self.ifacename, count)
-
- def axi_slave_idx(self, start, count):
- if not self.slow:
- return ('', 0)
- return self.slow.axi_slave_idx(start, self.ifacename, count)
+ def ifacedef2(self, *args):
+ res = '\n'.join(map(self.ifacedef2pin, self.pins))
+ res = res.format(*args)
+ return '\n' + res + '\n'
class MuxInterface(Interface):
return generic_io.format(*args)
-class Interfaces(InterfacesBase):
+class InterfaceBus(InterfaceFmt):
+
+ def __init__(self, pins, is_inout, namelist, bitspec, filterbus):
+ InterfaceFmt.__init__(self)
+ self.namelist = namelist
+ self.bitspec = bitspec
+ self.fbus = filterbus # filter identifying which are bus pins
+ self.pins_ = pins
+ self.is_inout = is_inout
+ self.buspins = filter(lambda x: x.name_.startswith(self.fbus),
+ self.pins_)
+ self.nonbuspins = filter(lambda x: not x.name_.startswith(self.fbus),
+ self.pins_)
+
+ def get_nonbuspins(self):
+ return self.nonbuspins
+
+ def get_buspins(self):
+ return self.buspins
+
+ def get_n_iopinsdiv(self):
+ return 3 if self.is_inout else 1
+
+ def ifacepfmt(self, *args):
+ pins = self.get_nonbuspins()
+ res = '\n'.join(map(self.ifacepfmtdecpin, pins)).format(*args)
+ res = res.format(*args)
+
+ pins = self.get_buspins()
+ plen = len(pins) / self.get_n_iopinsdiv()
+
+ res += '\n'
+ template = " interface {1}#(%s) {2};\n" % self.bitspec
+ for i, n in enumerate(self.namelist):
+ if not n:
+ continue
+ ftype = 'Get' if i == 2 else "Put"
+ res += template.format(plen, ftype, n)
+
+ return "\n" + res
+
+ def ifacedef2(self, *args):
+ pins = self.get_nonbuspins()
+ res = '\n'.join(map(self.ifacedef2pin, pins))
+ res = res.format(*args)
+
+ pins = self.get_buspins()
+ plen = len(pins) / self.get_n_iopinsdiv()
+ for pin in pins:
+ print "ifbus pins", pin.name_, plen
+ bitspec = self.bitspec.format(plen)
+ print self
+ return '\n' + res + self.vectorifacedef2(
+ pins, plen, self.namelist, bitspec, *args)
+
+ def ifacedef3pin(self, idx, pin):
+ decfn = self.ifacefmtdecfn2
+ outfn = self.ifacefmtoutfn
+ # print pin, pin.outenmode
+ if pin.outenmode:
+ decfn = self.ifacefmtdecfn3
+ outfn = self.ifacefmtoutenfn
+ return pin.ifacedef3(idx, outfn, self.ifacefmtinfn,
+ decfn)
+
+
+class InterfaceMultiBus(object):
+
+ def __init__(self, pins):
+ self.multibus_specs = []
+ self.nonbuspins = pins
+ self.nonb = self.add_bus(False, [], '', "xxxxxxxnofilter")
+
+ def add_bus(self, is_inout, namelist, bitspec, filterbus):
+ pins = self.nonbuspins
+ buspins = filter(lambda x: x.name_.startswith(filterbus), pins)
+ nbuspins = filter(lambda x: not x.name_.startswith(filterbus), pins)
+ self.nonbuspins = nbuspins
+ b = InterfaceBus(buspins, is_inout,
+ namelist, bitspec, filterbus)
+ print is_inout, namelist, filterbus, buspins
+ self.multibus_specs.append(b)
+ self.multibus_specs[0].pins_ = nbuspins
+ self.multibus_specs[0].nonbuspins = nbuspins
+
+ def ifacepfmt(self, *args):
+ res = ''
+ #res = Interface.ifacepfmt(self, *args)
+ for b in self.multibus_specs:
+ res += b.ifacepfmt(*args)
+ return res
+
+ def ifacedef2(self, *args):
+ res = ''
+ #res = Interface.ifacedef2(self, *args)
+ for b in self.multibus_specs:
+ res += b.ifacedef2(*args)
+ return res
+
+
+class InterfaceLCD(InterfaceBus, Interface):
+
+ def __init__(self, *args):
+ Interface.__init__(self, *args)
+ InterfaceBus.__init__(self, self.pins, False, ['data_out', None, None],
+ "Bit#({0})", "out")
+
+
+class InterfaceSDRAM(InterfaceMultiBus, Interface):
+
+ def __init__(self, ifacename, pinspecs, ganged=None, single=False):
+ Interface.__init__(self, ifacename, pinspecs, ganged, single)
+ InterfaceMultiBus.__init__(self, self.pins)
+ self.add_bus(False, ['dqm', None, None],
+ "Bit#({0})", "sdrdqm")
+ self.add_bus(True, ['d_out', 'd_out_en', 'd_in'],
+ "Bit#({0})", "sdrd")
+ self.add_bus(False, ['ad', None, None],
+ "Bit#({0})", "sdrad")
+ self.add_bus(False, ['ba', None, None],
+ "Bit#({0})", "sdrba")
+
+ def ifacedef2(self, *args):
+ return InterfaceMultiBus.ifacedef2(self, *args)
+
+
+class InterfaceFlexBus(InterfaceMultiBus, Interface):
+
+ def __init__(self, ifacename, pinspecs, ganged=None, single=False):
+ Interface.__init__(self, ifacename, pinspecs, ganged, single)
+ InterfaceMultiBus.__init__(self, self.pins)
+ self.add_bus(True, ['ad_out', 'ad_out_en', 'ad_in'],
+ "Bit#({0})", "ad")
+ self.add_bus(False, ['bwe', None, None],
+ "Bit#({0})", "bwe")
+ self.add_bus(False, ['tsiz', None, None],
+ "Bit#({0})", "tsiz")
+ self.add_bus(False, ['cs', None, None],
+ "Bit#({0})", "cs")
+
+ def ifacedef2(self, *args):
+ return InterfaceMultiBus.ifacedef2(self, *args)
+
+
+class InterfaceSD(InterfaceBus, Interface):
+
+ def __init__(self, *args):
+ Interface.__init__(self, *args)
+ InterfaceBus.__init__(self, self.pins, True, ['out', 'out_en', 'in'],
+ "Bit#({0})", "d")
+
+
+class InterfaceNSPI(InterfaceBus, Interface):
+
+ def __init__(self, *args):
+ Interface.__init__(self, *args)
+ InterfaceBus.__init__(self, self.pins, True,
+ ['io_out', 'io_out_en', 'io_in'],
+ "Bit#({0})", "io")
+
+
+class InterfaceEINT(Interface):
+ """ uses old-style (non-get/put) for now
+ """
+
+ def ifacepfmt(self, *args):
+ res = '\n'.join(map(self.ifacefmtdecpin, self.pins)).format(*args)
+ return '\n' + res # pins is a list
+
+ def ifacedef2(self, *args):
+ return self.ifacedef(*args)
+
+
+class InterfaceGPIO(InterfaceBus, Interface):
+ """ note: the busfilter cuts out everything as the entire set of pins
+ is a bus, but it's less code. get_nonbuspins returns empty list.
+ """
+
+ def __init__(self, ifacename, pinspecs, ganged=None, single=False):
+ Interface.__init__(self, ifacename, pinspecs, ganged, single)
+ InterfaceBus.__init__(self, self.pins, True, ['out', 'out_en', 'in'],
+ "Vector#({0},Bit#(1))", ifacename[-1])
+
+
+class Interfaces(InterfacesBase, PeripheralInterfaces):
""" contains a list of interface definitions
"""
def __init__(self, pth=None):
- InterfacesBase.__init__(self, Interface, pth)
+ InterfacesBase.__init__(self, Interface, pth,
+ {'gpio': InterfaceGPIO,
+ 'spi': InterfaceNSPI,
+ 'mspi': InterfaceNSPI,
+ 'lcd': InterfaceLCD,
+ 'sd': InterfaceSD,
+ 'fb': InterfaceFlexBus,
+ 'sdr': InterfaceSDRAM,
+ 'qspi': InterfaceNSPI,
+ 'mqspi': InterfaceNSPI,
+ 'eint': InterfaceEINT})
+ PeripheralInterfaces.__init__(self)
def ifacedef(self, f, *args):
for (name, count) in self.ifacecount:
for i in range(count):
f.write(self.data[name].ifacedef(i))
+ def ifacedef2(self, f, *args):
+ c = " interface {0} = interface PeripheralSide{1}"
+ for (name, count) in self.ifacecount:
+ for i in range(count):
+ iname = self.data[name].iname().format(i)
+ f.write(c.format(iname, name.upper()))
+ f.write(self.data[name].ifacedef2(i))
+ f.write(" endinterface;\n\n")
+
def busfmt(self, f, *args):
f.write("import BUtils::*;\n\n")
for (name, count) in self.ifacecount:
bf = self.data[name].busfmt(i)
f.write(bf)
+ def ifacepfmt(self, f, *args):
+ comment = '''
+ // interface declaration between {0} and pinmux
+ (*always_ready,always_enabled*)
+ interface PeripheralSide{0};'''
+ for (name, count) in self.ifacecount:
+ f.write(comment.format(name.upper()))
+ f.write(self.data[name].ifacepfmt(0))
+ f.write("\n endinterface\n")
+
def ifacefmt(self, f, *args):
comment = '''
// interface declaration between %s-{0} and pinmux'''
f.write(c.format(i))
f.write(self.data[name].ifacefmt(i))
+ def ifacefmt2(self, f, *args):
+ comment = '''
+ interface PeripheralSide{0} {1};'''
+ for (name, count) in self.ifacecount:
+ for i in range(count):
+ iname = self.data[name].iname().format(i)
+ f.write(comment.format(name.upper(), iname))
+
def wirefmt(self, f, *args):
comment = '\n // following wires capture signals ' \
'to IO CELL if %s-{0} is\n' \
f.write(c.format(i))
f.write(self.data[name].wirefmt(i))
- def slowimport(self, *args):
- ret = []
- for (name, count) in self.ifacecount:
- ret.append(self.data[name].slowimport())
- return '\n'.join(list(filter(None, ret)))
-
- def slowifdecl(self, *args):
- ret = []
- for (name, count) in self.ifacecount:
- for i in range(count):
- ret.append(self.data[name].slowifdecl(i))
- return '\n'.join(list(filter(None, ret)))
-
- def axi_reg_def(self, *args):
- ret = []
- start = 0x00011100 # start of AXI peripherals address
- for (name, count) in self.ifacecount:
- for i in range(count):
- x = self.data[name].axi_reg_def(start, i)
- print ("ifc", name, x)
- (rdef, offs) = x
- ret.append(rdef)
- start += offs
- return '\n'.join(list(filter(None, ret)))
-
- def axi_slave_idx(self, *args):
- ret = []
- start = 0
- for (name, count) in self.ifacecount:
- for i in range(count):
- (rdef, offs) = self.data[name].axi_slave_idx(start, i)
- print ("ifc", name, rdef, offs)
- ret.append(rdef)
- start += offs
- ret.append("typedef %d LastGen_slave_num" % (start-1))
- decls = '\n'.join(list(filter(None, ret)))
- return axi_slave_declarations.format(decls)
-
# ========= Interface declarations ================ #
projects / pinmux.git / blobdiff