if not irqname:
return ''
pirqname = self.irq_name().format(count)
- template = " {0}_interrupt.send(\n" + \
+ template = " {0}.send(\n" + \
" slow_peripherals.{1});"
return template.format(irqname, pirqname)
name = self.axi_slave_name(name, ifacenum, typ)
return ("typedef {0} {1};".format(idx, name), 1)
- def axi_addr_map(self, name, ifacenum):
+ def axi_fastaddr_map(self, name, ifacenum):
+ return self.axi_addr_map(name, ifacenum, 'fast')
+
+ def axi_addr_map(self, name, ifacenum, typ=""):
bname = self.axibase(name, ifacenum)
bend = self.axiend(name, ifacenum)
- name = self.axi_slave_name(name, ifacenum)
+ name = self.axi_slave_name(name, ifacenum, typ)
template = """\
if(addr>=`{0} && addr<=`{1})
return tuple2(True,fromInteger(valueOf({2})));
else"""
return template.format(bname, bend, name)
- def mk_pincon(self, name, count):
+ def _mk_pincon(self, name, count, ptyp):
# TODO: really should be using bsv.interface_decl.Interfaces
# pin-naming rules.... logic here is hard-coded to duplicate
# it (see Interface.__init__ outen)
#n = "{0}{1}".format(self.name, self.mksuffix(name, count))
n = name # "{0}{1}".format(self.name, self.mksuffix(name, count))
ret.append("//%s %s" % (n, str(p)))
- sname = self.peripheral.iname().format(count)
- sname = "{0}.{1}".format(sname, pname)
- ps = "pinmux.peripheral_side.%s" % sname
+ if ptyp == 'fast':
+ sname = self.get_iname(count)
+ sname = "{0}.{1}".format(sname, pname)
+ ps = "slow_peripherals.%s" % sname
+ else:
+ sname = self.peripheral.iname().format(count)
+ sname = "{0}.{1}".format(sname, pname)
+ ps = "pinmux.peripheral_side.%s" % sname
if typ == 'out' or typ == 'inout':
fname = self.pinname_out(pname)
if not n.startswith('gpio'): # XXX EURGH! horrible hack
ps_ = ps + '_out'
else:
ps_ = ps
- ret.append("mkConnection({0},\n\t\t\t{1}.{2});"
- .format(ps_, n_, fname))
+ cn = self._mk_actual_connection('out', name,
+ count, typ,
+ pname, ps_, n_, fname)
+ ret += cn
fname = None
if p.get('outen'):
fname = self.pinname_outen(pname)
if isinstance(fname, str):
fname = "{0}.{1}".format(n_, fname)
fname = self.pinname_tweak(pname, 'outen', fname)
- ret.append("mkConnection({0}_outen,\n\t\t\t{1});"
- .format(ps, fname))
+ cn = self._mk_actual_connection('outen', name,
+ count, typ,
+ pname, ps, n, fname)
+ ret += cn
if typ == 'in' or typ == 'inout':
fname = self.pinname_in(pname)
if fname:
n_ = "{0}{1}".format(n, count)
n_ = '{0}.{1}'.format(n_, fname)
n_ = self.ifname_tweak(pname, 'in', n_)
- ret.append(
- "mkConnection({1},\n\t\t\t{0});".format(
- ps_, n_))
+ cn = self._mk_actual_connection('in', name,
+ count, typ,
+ pname, ps_, n_, fname)
+ ret += cn
+ return '\n'.join(ret)
+
+ def _mk_vpincon(self, name, count, ptyp, typ, pname, stype=None):
+ if stype is None:
+ stype = pname
+ ret = []
+ ret.append("//%s %s %s %s %s" % (name, ptyp, typ, pname, stype))
+ if ptyp == 'fast':
+ sname = self.get_iname(count)
+ ps = "slow_peripherals.%s" % sname
+ else:
+ sname = self.peripheral.iname().format(count)
+ ps = "pinmux.peripheral_side.%s" % sname
+ n = self.get_iname(count)
+ if typ == 'in':
+ n = "{0}.{1}".format(n, stype)
+ ps_ = "{0}.{1}".format(ps, pname)
+ ret += self._mk_actual_connection(typ, name, count, typ,
+ pname, ps_, n, stype)
+ return '\n'.join(ret)
+
+ def _mk_actual_connection(self, ctype, name, count, typ,
+ pname, ps, n, fname):
+ ret = []
+ ck = self.get_clock_reset(name, count)
+ if ctype == 'out':
+ if ck == PBase.get_clock_reset(self, name, count):
+ ret.append("mkConnection({0},\n\t\t\t{1}.{2});"
+ .format(ps, n, fname))
+ else:
+ n2 = "{0}{1}".format(name, count)
+ sync = '{0}_{1}_sync'.format(n2, pname)
+ ret.append("mkConnection({0},\n\t\t\t{1}.get);"
+ .format(ps, sync))
+ ret.append("mkConnection({0}.put,\n\t\t\t{1}.{2});"
+ .format(sync, n, fname))
+ elif ctype == 'outen':
+ ret.append("mkConnection({0}_outen,\n\t\t\t{1});"
+ .format(ps, fname))
+ elif ctype == 'in':
+ if ck == PBase.get_clock_reset(self, name, count):
+ ret.append("mkConnection({1},\n\t\t\t{0});".format(
+ ps, n))
+ else:
+ n2 = "{0}{1}".format(name, count)
+ sync = '{0}_{1}_sync'.format(n2, pname)
+ ret.append("mkConnection({1}.put,\n\t\t\t{0});".format(
+ ps, sync))
+ ret.append("mkConnection({1},\n\t\t\t{0}.get);".format(
+ sync, n))
+ return ret
+
+
+ def _mk_clk_con(self, name, count, ctype):
+ ret = []
+ ck = self.get_clock_reset(name, count)
+ if ck == PBase.get_clock_reset(self, name, count):
+ return ''
+ if ctype == 'slow':
+ spc = self.get_clk_spc(ctype)
+ else:
+ spc = ck
+ ck = self.get_clk_spc(ctype)
+ template = """\
+Ifc_sync#({0}) {1}_sync <-mksyncconnection(
+ {2}, {3});"""
+ for p in self.peripheral.pinspecs:
+ typ = p['type']
+ pname = p['name']
+ n = name
+ if typ == 'out' or typ == 'inout':
+ fname = self.pinname_out(pname)
+ if not fname:
+ continue
+ if not n.startswith('gpio'): # XXX EURGH! horrible hack
+ n_ = "{0}{1}".format(n, count)
+ else:
+ n_ = n
+ n_ = '{0}_{1}'.format(n_, pname)
+ ret.append(template.format("Bit#(1)", n_, ck, spc))
+ if typ == 'in' or typ == 'inout':
+ fname = self.pinname_in(pname)
+ if not fname:
+ continue
+ #fname = self.pinname_in(pname)
+ n_ = "{0}{1}".format(n, count)
+ n_ = '{0}_{1}'.format(n_, pname)
+ #n_ = self.ifname_tweak(pname, 'in', n_)
+ ret.append(template.format("Bit#(1)", n_, spc, ck))
return '\n'.join(ret)
+ def get_clk_spc(self, ctype):
+ if ctype == 'slow':
+ return "sp_clock, sp_reset"
+ else:
+ return "core_clock, core_reset"
+
+ def _mk_clk_vcon(self, name, count, ctype, typ, pname, bitspec):
+ ck = self.get_clock_reset(name, count)
+ if ck == PBase.get_clock_reset(self, name, count):
+ return ''
+ if ctype == 'slow':
+ spc = self.get_clk_spc(ctype)
+ else:
+ spc = ck
+ ck = self.get_clk_spc(ctype)
+ template = """\
+Ifc_sync#({0}) {1}_sync <-mksyncconnection(
+ {2}, {3});"""
+
+ n_ = "{0}{1}".format(name, count)
+ n_ = '{0}_{1}'.format(n_, pname)
+ if typ == 'in' or typ == 'inout':
+ ck, spc = spc, ck
+ return template.format(bitspec, n_, ck, spc)
+
+
def mk_cellconn(self, *args):
return ''
return ''
return txt.format(con, aname, fabricname)
- def __mk_master_connection(self, con, aname):
- txt = "mkConnection (slow_fabric.v_to_slaves\n" + \
- " [fromInteger(valueOf({1}))],\n" + \
- " {0});"
+ def __mk_master_connection(self, con, aname, fabricname):
+ txt = "mkConnection ({0}, {2}.v_from_masters\n" + \
+ " [fromInteger(valueOf({1}))]);\n"
- print "PBase __mk_connection", self.name, aname
+ print "PBase __mk_master_connection", self.name, aname
if not con:
return ''
- return txt.format(con, aname)
+ return txt.format(con, aname, fabricname)
+
+ def mk_master_connection(self, count, fabricname, typ, name=None):
+ if not self.has_axi_master():
+ return ''
+ if name is None:
+ name = self.name
+ print "PBase mk_master_conn", self.name, count
+ aname = self.axi_master_name(name, count, typ)
+ con = self._mk_connection(name, count, True).format(count, aname)
+ return self.__mk_master_connection(con, aname, fabricname)
def mk_connection(self, count, fabricname, typ, name=None):
if name is None:
name = self.name
print "PBase mk_conn", self.name, count
aname = self.axi_slave_name(name, count, typ)
- #dname = self.mksuffix(name, count)
- #dname = "{0}{1}".format(name, dname)
con = self._mk_connection(name, count).format(count, aname)
return self.__mk_connection(con, aname, fabricname)
axi_fastslave_declarations = """\
{0}
-typedef TAdd#(LastGen_fastslave_num,1) Sdram_cfg_slave_num;
+typedef TAdd#(LastGen_fastslave_num,1) Sdram_slave_num;
typedef TAdd#(Sdram_slave_num ,`ifdef SDRAM 1 `else 0 `endif )
Sdram_cfg_slave_num;
typedef TAdd#(Sdram_cfg_slave_num,`ifdef BOOTROM 1 `else 0 `endif )
Debug_slave_num ;
typedef TAdd#(Debug_slave_num , `ifdef TCMemory 1 `else 0 `endif )
TCM_slave_num;
-typedef TAdd#(TCM_slave_num ,`ifdef DMA 1 `else 0 `endif )
+typedef TAdd#(TCM_slave_num ,`ifdef DMA 1 `else 0 `endif )
Dma_slave_num;
typedef TAdd#(Dma_slave_num ,1 ) SlowPeripheral_slave_num;
typedef TAdd#(SlowPeripheral_slave_num,`ifdef VME 1 `else 0 `endif )
VME_slave_num;
-typedef TAdd#(VME_slave_num,`ifdef FlexBus 1 `else 0 `endif )
- FlexBus_slave_num;
-typedef TAdd#(FlexBus_slave_num,1)
- Num_Slaves;
-
+typedef TAdd#(VME_slave_num,1) Num_Fast_Slaves;
"""
axi_slave_declarations = """\
'mk_dma_sync', 'mk_dma_connect', 'mk_dma_rule',
'mkfast_peripheral',
'mk_plic', 'mk_ext_ifacedef',
- 'mk_connection', 'mk_cellconn', 'mk_pincon']:
+ '_mk_clk_con', 'mk_ext_ifacedef',
+ 'mk_connection', 'mk_master_connection',
+ 'mk_cellconn', '_mk_pincon']:
fn = CallFn(self, fname)
setattr(self, fname, types.MethodType(fn, self))
return ('', 0)
return self.slow.axi_slave_idx(start, self.ifacename, count, typ)
+ def axi_fastaddr_map(self, count):
+ if not self.slow:
+ return ''
+ return self.slow.axi_fastaddr_map(self.ifacename, count)
+
def axi_addr_map(self, count):
if not self.slow:
return ''
return self._axi_num_idx(0, axi_fastslave_declarations, 'fastslave',
'fast', *args)
+ def axi_fastaddr_map(self, *args):
+ ret = []
+ for (name, count) in self.ifacecount:
+ for i in range(count):
+ if self.is_on_fastbus(name, i):
+ continue
+ ret.append(self.data[name].axi_fastaddr_map(i))
+ return '\n'.join(li(list(filter(None, ret)), 8))
+
def axi_addr_map(self, *args):
ret = []
for (name, count) in self.ifacecount:
ret.append(x.format(suffix))
return '\n'.join(li(list(filter(None, ret)), 8))
- def mk_fast_connection(self, *args):
+ def _mk_connection(self, fabric, typ, indent, master, *args):
ret = []
for (name, count) in self.ifacecount:
for i in range(count):
if self.is_on_fastbus(name, i):
continue
- txt = self.data[name].mk_connection(i, "fabric", "fast")
+ if master:
+ txt = self.data[name].mk_master_connection(i, fabric, typ)
+ else:
+ txt = self.data[name].mk_connection(i, fabric, typ)
if name == 'gpioa':
print "txt", txt
- print self.data[name].mk_connection
ret.append(txt)
- return '\n'.join(li(list(filter(None, ret)), 12))
+ return '\n'.join(li(list(filter(None, ret)), indent))
+
+ def mk_master_connection(self, *args):
+ return self._mk_connection("fabric", "fast", 8, True, *args)
+
+ def mk_fast_connection(self, *args):
+ return self._mk_connection("fabric", "fast", 12, False, *args)
def mk_connection(self, *args):
- ret = []
- for (name, count) in self.ifacecount:
- for i in range(count):
- if self.is_on_fastbus(name, i):
- continue
- txt = self.data[name].mk_connection(i, "slow_fabric", "")
- if name == 'gpioa':
- print "txt", txt
- print self.data[name].mk_connection
- ret.append(txt)
- return '\n'.join(li(list(filter(None, ret)), 8))
+ return self._mk_connection("slow_fabric", "", 8, False, *args)
def mk_cellconn(self):
ret = []
return li(pinmux_cellrule.format(ret), 4)
def mk_pincon(self):
+ return self._mk_pincon("slow")
+
+ def mk_fast_pincon(self):
+ return self._mk_pincon("fast")
+
+ def _mk_pincon(self, typ):
ret = []
for (name, count) in self.ifacecount:
for i in range(count):
if self.is_on_fastbus(name, i):
continue
- txt = self.data[name].mk_pincon(name, i)
+ txt = self.data[name]._mk_pincon(name, i, typ)
ret.append(txt)
return '\n'.join(li(list(filter(None, ret)), 4))
def mk_sloirqsdef(self):
return " `define NUM_SLOW_IRQS {0}".format(self.num_slow_irqs)
+ def mk_fastclk_con(self):
+ return self._mk_clk_con("fast")
+
+ def mk_slowclk_con(self):
+ return self._mk_clk_con("slow")
+
+ def _mk_clk_con(self, ctype):
+ ret = []
+ for (name, count) in self.ifacecount:
+ for i in range(count):
+ if self.is_on_fastbus(name, i):
+ continue
+ txt = self.data[name]._mk_clk_con(name, i, ctype)
+ ret.append(txt)
+ return '\n'.join(li(list(filter(None, ret)), 8))
+
def is_on_fastbus(self, name, i):
#print "fastbus mode", self.fastbusmode, name, i
iname = self.data[name].iname().format(i)
'spi': spi,
'pwm': pwm,
'eint': eint,
- 'sd': sdmmc,
+ 'mmc': sdmmc,
'jtag': jtag,
'lcd': rgbttl,
'fb': flexbus,
projects / pinmux.git / blobdiff