return res
-class PBase(object):
+class MMapConfig(object):
+
+ def get_mmap_configs(self):
+ res = []
+ for cfg in self.peripheral.configs:
+ res.append(cfg.get('mmap', None))
+ # XXX HACK! assume all configs same for each peripheral!
+ return res[0]
+
+ def map_to_idx(self, cfg, idx):
+ if isinstance(idx, int):
+ return idx
+ for (i, c) in enumerate(cfg):
+ if c[0] == idx:
+ return i
+ assert "config name %s not found" % s
+
+ def get_mmap_cfg_start(self, idx):
+ cfg = self.get_mmap_configs()
+ if cfg is None:
+ nregs = self.num_axi_regs32()
+ if isinstance(nregs, int) or len(nregs) == 1:
+ return 0
+ return "_%d_" % idx
+ idx = self.map_to_idx(cfg, idx)
+ return cfg[idx][1]
+
+ def get_mmap_cfg_name(self, idx):
+ cfg = self.get_mmap_configs()
+ if cfg is None:
+ nregs = self.num_axi_regs32()
+ if isinstance(nregs, int) or len(nregs) == 1:
+ return ""
+ return "_%d_" % idx
+ return cfg[idx][0]
+
+ def num_axi_regs32cfg(self):
+ cfg = self.get_mmap_configs()
+ if cfg is None:
+ return self.num_axi_regs32()
+ regs = []
+ for c in cfg:
+ regs.append(c[2])
+ return regs
+
+
+class PBase(MMapConfig):
def __init__(self, name):
self.name = name
+ MMapConfig.__init__(self)
def extifdecl(self, name, count):
sname = self.get_iname(count)
def slowimport(self):
return ''
- def get_mmap_configs(self):
- res = []
- for cfg in self.peripheral.configs:
- res.append(cfg.get('mmap', None))
- # XXX HACK! assume all configs same for each peripheral!
- return res[0]
-
- def get_mmap_cfg_name(self, idx):
- cfg = self.get_mmap_configs()
- if cfg is None:
- nregs = self.num_axi_regs32()
- if isinstance(nregs, int) or len(nregs) == 1:
- return ""
- return "_%d_" % idx
- return cfg[idx][0]
-
- def num_axi_regs32cfg(self):
- cfg = self.get_mmap_configs()
- if cfg is None:
- return self.num_axi_regs32()
- regs = []
- for c in cfg:
- regs.append(c[2])
- return regs
-
def num_axi_regs32(self):
return 0
offs = numregs * 4 * 16
if offs == 0:
return ('', 0)
- end = start + offs - 1
+ cfgstart = self.get_mmap_cfg_start(idx)
+ if cfgstart:
+ start = cfgstart
+ end = start + offs - 1
+ offs = 0 # don't do contiguous addressing
+ else:
+ end = start + offs - 1
bname = self.axibase(name, ifacenum, idx)
bend = self.axiend(name, ifacenum, idx)
comment = "%d 32-bit regs" % numregs
- return (" `define %(bname)s 'h%(start)08X\n"
- " `define %(bend)s 'h%(end)08X // %(comment)s" % locals(),
+ return ("`define %(bname)s 'h%(start)08X\n"
+ "`define %(bend)s 'h%(end)08X // %(comment)s" % locals(),
offs)
def axi_reg_def(self, start, name, ifacenum):
else:
spc = ck
ck = self.get_clk_spc(ctype)
- template = """\
-Ifc_sync#({0}) {1}_sync <-mksyncconnection(
- {2}, {3});"""
+ template = "Ifc_sync#({0}) {1}_sync <-mksyncconnection(\n" + \
+ " {2}, {3});"
for p in self.peripheral.pinspecs:
typ = p['type']
pname = p['name']
else:
spc = ck
ck = self.get_clk_spc(ctype)
- template = """\
-Ifc_sync#({0}) {1}_sync <-mksyncconnection(
- {2}, {3});"""
+ template = "Ifc_sync#({0}) {1}_sync <-mksyncconnection(\n" + \
+ " {2}, {3});"""
n_ = "{0}{1}".format(name, count)
n_ = '{0}_{1}'.format(n_, pname)
if not isinstance(connections, list):
connections = [connections]
for (idx, con) in enumerate(connections):
- if len(connections) == 1:
- idx = ""
- else:
- idx = "_%d_" % idx
- aname = self.axi_slave_name(idx, name, count, typ)
+ cfg = self.get_mmap_cfg_name(idx)
+ aname = self.axi_slave_name(cfg, name, count, typ)
ret.append(self.__mk_connection(con, aname, count, fabricname))
return '\n'.join(ret)
ret = []
for (name, count) in self.ifacecount:
for i in range(count):
- iname = self.data[name].iname().format(i)
- print "extfast", iname, self.is_on_fastbus(name, i)
if self.is_on_fastbus(name, i):
continue
ret.append(self.data[name].extfastifinstance(name, i))
ret = []
for (name, count) in self.ifacecount:
for i in range(count):
- iname = self.data[name].iname().format(i)
ret.append(self.data[name].extifinstance2(name, i))
return '\n'.join(li(list(filter(None, ret)), 8))
ret = []
for (name, count) in self.ifacecount:
for i in range(count):
- iname = self.data[name].iname().format(i)
if not self.is_on_fastbus(name, i):
continue
ret.append(self.data[name].extifinstance(name, i))
from uart import uart
from quart import quart
from sdmmc import sdmmc
+ from emmc import emmc
from pwm import pwm
from eint import eint
from rs232 import rs232
'pwm': pwm,
'eint': eint,
'mmc': sdmmc,
+ 'emmc': emmc,
'jtag': jtag,
'lcd': rgbttl,
'fb': flexbus,