add sdram dual axi4 configs

[pinmux.git] / src / bsv / peripheral_gen / jtag.py

diff --git a/src/bsv/peripheral_gen/jtag.py b/src/bsv/peripheral_gen/jtag.py
index d8e63de3975d2de4e23ea8f7c6681d149567bdf7..e5f5e2ad3cdb512b69cb983f811ab0e08eaf2d82 100644 (file)
--- a/src/bsv/peripheral_gen/jtag.py
+++ b/src/bsv/peripheral_gen/jtag.py
@@ -4,14 +4,30 @@ from bsv.peripheral_gen.base import PBase
 class jtag(PBase):
 
     def slowimport(self):
-        return "import jtagtdm::*;\n"
+        return "import jtagdtm::*;\n"
 
     def extfastifinstance(self, name, count):
         return self._extifinstance(name, count, "_out", "", True)
 
     def fastifdecl(self, name, count):
         # YUK!
-        return "Ifc_jtagdtm jtag{0}_out;".format(count)
+        return "interface Ifc_jtagdtm jtag{0}_out;".format(count)
+
+    def get_clk_spc(self, typ):
+        return "tck, trst"
+
+    def get_clock_reset(self, name, count):
+        return "slow_clock,  slow_reset"
+
+    def pinname_in(self, pname):
+        return {'tms': 'tms',
+                'tdi': 'tdi',
+                }.get(pname, '')
+
+    def pinname_out(self, pname):
+        return {'tck': 'tck',
+                'tdo': 'tdo',
+                }.get(pname, '')
 
     def mkfast_peripheral(self):
         return """\
@@ -25,11 +41,11 @@ rule drive_tmp_scan_outs;
 endrule
 """
 
-    def axi_slave_name(self, name, ifacenum, typ=''):
+    def axi_slave_name(self, idx, name, ifacenum, typ=None):
         return ''
 
     def axi_slave_idx(self, idx, name, ifacenum, typ):
         return ('', 0)
 
-    def axi_addr_map(self, name, ifacenum):
+    def axi_addr_map(self, name, ifacenum, typ=None):
         return ''