add sdram dual axi4 configs

[pinmux.git] / src / bsv / peripheral_gen / sdram.py

diff --git a/src/bsv/peripheral_gen/sdram.py b/src/bsv/peripheral_gen/sdram.py
index baf355d0dc455de0770d51ccbc9604fa7738716a..7002d6a4b73a8f257c8071ba318578cc0431cff5 100644 (file)
--- a/src/bsv/peripheral_gen/sdram.py
+++ b/src/bsv/peripheral_gen/sdram.py
@@ -4,28 +4,30 @@ from bsv.peripheral_gen.base import PBase
 class sdram(PBase):
 
     def slowimport(self):
-        return "import FlexBus_Types::*;"
+        return "import sdr_top::*;"
 
     def num_axi_regs32(self):
-        return 0x400000  # defines an entire memory range
+        return [0x400000,  # defines an entire memory range (hack...)
+                12]        # defines the number of configuration regs
 
     def extfastifinstance(self, name, count):
         return "// TODO" + self._extifinstance(name, count, "_out", "", True,
-                                   ".sdram_side")
+                                   ".if_sdram_out")
 
     def fastifdecl(self, name, count):
-        return "//interface FlexBus_Master_IFC fb{0}_out;".format(count)
+        return "// (*always_ready*) interface " + \
+                "Ifc_sdram_out sdr{0}_out;".format(count)
 
     def get_clock_reset(self, name, count):
         return "slow_clock, slow_reset"
 
     def mkfast_peripheral(self):
-        return "AXI4_Slave_to_FlexBus_Master_Xactor_IFC " + \
-               "#(`PADDR, `DATA, `USERSPACE)\n" + \
-               "        fb{0} <- mkAXI4_Slave_to_FlexBus_Master_Xactor;"
+        return "Ifc_sdr_slave sdr{0} <- mksdr_axi4_slave(clk0);"
 
     def _mk_connection(self, name=None, count=0):
-        return "fb{0}.axi_side"
+        return ["sdr{0}.axi4_slave_sdram",
+                "sdr{0}.axi4_slave_cntrl_reg"]
+                
 
     def pinname_in(self, pname):
         return {'ta': 'sdram_side.m_tAn',