return "import sdr_top::*;"
def num_axi_regs32(self):
- return 0x400000 # defines an entire memory range
+ return [0x400000, # defines an entire memory range (hack...)
+ 12] # defines the number of configuration regs
def extfastifinstance(self, name, count):
return "// TODO" + self._extifinstance(name, count, "_out", "", True,
- ".sdram_side")
+ ".if_sdram_out")
def fastifdecl(self, name, count):
- return "//interface FlexBus_Master_IFC sdr{0}_out;".format(count)
+ return "// (*always_ready*) interface " + \
+ "Ifc_sdram_out sdr{0}_out;".format(count)
def get_clock_reset(self, name, count):
return "slow_clock, slow_reset"
return "Ifc_sdr_slave sdr{0} <- mksdr_axi4_slave(clk0);"
def _mk_connection(self, name=None, count=0):
- return "sdr{0}.axi_side"
+ return ["sdr{0}.axi4_slave_sdram",
+ "sdr{0}.axi4_slave_cntrl_reg"]
+
def pinname_in(self, pname):
return {'ta': 'sdram_side.m_tAn',