try different clock combination

[pinmux.git] / src / bsv / peripheral_gen / sdram.py

diff --git a/src/bsv/peripheral_gen/sdram.py b/src/bsv/peripheral_gen/sdram.py
index 79a9741f9f86a4b878baea62eaca750ae60f162d..ce6ba4364e43fd3492b531e64389c13434afa2fa 100644 (file)
--- a/src/bsv/peripheral_gen/sdram.py
+++ b/src/bsv/peripheral_gen/sdram.py
@@ -18,6 +18,9 @@ class sdram(PBase):
         return "// (*always_ready*) interface " + \
                 "Ifc_sdram_out sdr{0}_out;".format(count)
 
+    def get_clk_spc(self, typ):
+        return "clk0, slow_reset"
+
     def get_clock_reset(self, name, count):
         return "slow_clock, slow_reset"
 
@@ -32,6 +35,7 @@ class sdram(PBase):
         return {'sdrwen': 'ifc_sdram_out.osdr_we_n',
                 'sdrcsn0': 'ifc_sdram_out.osdr_cs_n',
                 'sdrcke': 'ifc_sdram_out.osdr_cke',
+                'sdrclk': 'ifc_sdram_out.osdr_clock',
                 'sdrrasn': 'ifc_sdram_out.osdr_ras_n',
                 'sdrcasn': 'ifc_sdram_out.osdr_cas_n',
                 }.get(pname, '')
@@ -39,12 +43,12 @@ class sdram(PBase):
     def _mk_clk_con(self, name, count, ctype):
         ret = [PBase._mk_clk_con(self, name, count, ctype)]
         for pname, sz, ptype in [
-            ('cs', 6, 'out'),
-            ('bwe', 4, 'out'),
-            ('tsiz', 2, 'out'),
-            ('ad_out', 32, 'out'),
-            ('ad_in', 32, 'in'),
-            ('ad_out_en', 32, 'out'),
+            ('dqm', 8, 'out'),
+            ('ba', 2, 'out'),
+            ('ad', 13, 'out'),
+            ('d_out', 64, 'out'),
+            ('d_in', 64, 'in'),
+            ('d_out_en', 64, 'out'),
         ]:
             bitspec = "Bit#(%d)" % sz
             txt = self._mk_clk_vcon(name, count, ctype, ptype, pname, bitspec)
@@ -55,14 +59,14 @@ class sdram(PBase):
         ret = [PBase._mk_pincon(self, name, count, typ)]
         assert typ == 'fast' # TODO slow?
         for pname, stype, ptype in [
-            ('cs', 'm_FBCSn', 'out'),
-            ('bwe', 'm_BWEn', 'out'),
-            ('tsiz', 'm_TSIZ', 'out'),
-            ('ad_out', 'm_AD', 'out'),
-            ('ad_in', 'm_din', 'in'),
-            ('ad_out_en', 'm_OE32n', 'out'),
+            ('dqm', 'osdr_dqm', 'out'),
+            ('ba', 'osdr_ba', 'out'),
+            ('ad', 'osdr_addr', 'out'),
+            ('d_out', 'osdr_dout', 'out'),
+            ('d_in', 'ipad_sdr_din', 'in'),
+            ('d_out_en', 'osdr_den_n', 'out'),
         ]:
             ret.append(self._mk_vpincon(name, count, typ, ptype, pname,
-                                        "sdram_side.{0}".format(stype)))
+                                        "ifc_sdram_out.{0}".format(stype)))
 
         return '\n'.join(ret)