whoops name wrong

[pinmux.git] / src / spec / pinfunctions.py

diff --git a/src/spec/pinfunctions.py b/src/spec/pinfunctions.py
index 15b0cb501bf0e49dd4ddbb5ab0c4e4f9f0f32240..c09eb1cff771fe26ad9f2dc113adf05f70b832c8 100644 (file)
--- a/src/spec/pinfunctions.py
+++ b/src/spec/pinfunctions.py
@@ -2,8 +2,10 @@
 
 """ define functions here, with their pin names and the pin type.
 
-    each function returns a list (or an object with a __getitem__ function)
-    containing pin name plus type specifications.
+    each function returns a pair of lists
+    (or objects with a __getitem__ function)
+
+    the first list (or object) contains pin name plus type specifications.
 
     the type is:
 
@@ -25,6 +27,18 @@
     generated, and that's not known immediately (or it would be if
     every single one of the functions below had a start and end parameter
     added).  see spec.interfaces.PinGen class slice on pingroup
+
+    the second list is the names of pins that are part of an inout bus.
+    this list of pins (a ganged group) will need to be changed under
+    the control of the function, as a group.  for example: sdmmc's
+    D0-D3 pins are in-out, they all change from input to output at
+    the same time under the control of the function, therefore there's
+    no point having multiple in-out switch/control wires, as the
+    sdmmc is never going to do anything other than switch this entire
+    bank all at once.  so in this particular example, sdmmc returns:
+
+        (['CMD+', 'CLK+', 'D0*', 'D1*', 'D2*', 'D3*'] # pin names
+         ['D0*', 'D1*', 'D2*', 'D3*'])                # ganged bus names
 """
 
 
@@ -47,27 +61,41 @@ def sdmmc(suffix, bank):
     return emmc(suffix, bank, pincount=4)
 
 
-def spi(suffix, bank):
-    pins = ['CLK*', 'NSS*', 'MOSI*', 'MISO*']
-    return (pins, [])
-
-
-def quadspi(suffix, bank):
-    qpins = ['CK*', 'NSS*']
+def nspi(suffix, bank, iosize, masteronly=True):
+    if masteronly:
+        qpins = ['CK+', 'NSS+']
+    else:
+        qpins = ['CK*', 'NSS*']
     inout = []
-    for i in range(4):
+    for i in range(iosize):
         pname = "IO%d*" % i
         qpins.append(pname)
         inout.append(pname)
     return (qpins, inout)
 
 
+def mspi(suffix, bank):
+    return nspi(suffix, bank, 2, masteronly=True)
+
+
+def mquadspi(suffix, bank):
+    return nspi(suffix, bank, 4, masteronly=True)
+
+
+def spi(suffix, bank):
+    return nspi(suffix, bank, 2)
+
+
+def quadspi(suffix, bank):
+    return nspi(suffix, bank, 4)
+
+
 def i2c(suffix, bank):
     return (['SDA*', 'SCL*'], [])
 
 
 def jtag(suffix, bank):
-    return (['MS+', 'DI-', 'DO+', 'CK+'], [])
+    return (['TMS-', 'TDI-', 'TDO+', 'TCK+'], [])
 
 
 def uart(suffix, bank):
@@ -89,7 +117,7 @@ def uartfull(suffix, bank):
 def rgbttl(suffix, bank):
     ttlpins = ['CK+', 'DE+', 'HS+', 'VS+']
     for i in range(24):
-        ttlpins.append("D%d+" % i)
+        ttlpins.append("OUT%d+" % i)
     return (ttlpins, [])
 
 
@@ -115,11 +143,12 @@ def flexbus1(suffix, bank):
         inout.append(pname)
     for i in range(2):
         buspins.append("CS%d+" % i)
-    buspins += ['ALE', 'OE', 'RW', 'TA', 'CLK+',
-                'A0', 'A1', 'TS', 'TBST',
-                'TSIZ0', 'TSIZ1']
+    buspins += ['ALE+', 'OE+', 'RW+', 'TA-',
+                # 'TS+',  commented out for now, mirrors ALE, for mux'd mode
+                'TBST+',
+                'TSIZ0+', 'TSIZ1+']
     for i in range(4):
-        buspins.append("BWE%d" % i)
+        buspins.append("BWE%d+" % i)
     for i in range(2, 6):
         buspins.append("CS%d+" % i)
     return (buspins, inout)
@@ -135,33 +164,45 @@ def flexbus2(suffix, bank):
 def sdram1(suffix, bank):
     buspins = []
     inout = []
-    for i in range(16):
+    for i in range(8):
         pname = "SDRDQM%d*" % i
         buspins.append(pname)
+    for i in range(8):
+        pname = "SDRD%d*" % i
+        buspins.append(pname)
         inout.append(pname)
     for i in range(12):
         buspins.append("SDRAD%d+" % i)
-    for i in range(8):
-        buspins.append("SDRDQ%d+" % i)
-    for i in range(3):
-        buspins.append("SDRCS%d#+" % i)
-    for i in range(2):
-        buspins.append("SDRDQ%d+" % i)
     for i in range(2):
         buspins.append("SDRBA%d+" % i)
-    buspins += ['SDRCKE+', 'SDRRAS#+', 'SDRCAS#+', 'SDRWE#+',
-                'SDRRST+']
+    buspins += ['SDRCKE+', 'SDRRASn+', 'SDRCASn+', 'SDRWEn+',
+                'SDRCSn0+']
     return (buspins, inout)
 
 
 def sdram2(suffix, bank):
     buspins = []
     inout = []
-    for i in range(3, 6):
-        buspins.append("SDRCS%d#+" % i)
-    for i in range(16, 32):
+    for i in range(1, 6):
+        buspins.append("SDRCSn%d+" % i)
+    for i in range(8, 16):
         pname = "SDRDQM%d*" % i
         buspins.append(pname)
+    for i in range(8, 16):
+        pname = "SDRD%d*" % i
+        buspins.append(pname)
+        inout.append(pname)
+    return (buspins, inout)
+
+
+def sdram3(suffix, bank):
+    buspins = []
+    inout = []
+    for i in range(12, 13):
+        buspins.append("SDRAD%d+" % i)
+    for i in range(8, 64):
+        pname = "SDRD%d*" % i
+        buspins.append(pname)
         inout.append(pname)
     return (buspins, inout)
 
@@ -197,7 +238,7 @@ class RangePin(object):
 
 
 def eint(suffix, bank):
-    return (RangePin("*"), [])
+    return (RangePin("-"), [])
 
 
 def pwm(suffix, bank):
@@ -213,12 +254,14 @@ def gpio(suffix, bank):
 pinspec = (('IIS', i2s),
            ('MMC', emmc),
            ('SD', sdmmc),
+           ('MSPI', mspi),
+           ('MQSPI', mquadspi),
            ('SPI', spi),
            ('QSPI', quadspi),
            ('TWI', i2c),
            ('JTAG', jtag),
            ('UART', uart),
-           ('UARTQ', uartfull),
+           ('QUART', uartfull),
            ('LCD', rgbttl),
            ('ULPI', ulpi),
            ('RG', rgmii),
@@ -226,6 +269,7 @@ pinspec = (('IIS', i2s),
            ('FB', flexbus2),
            ('SDR', sdram1),
            ('SDR', sdram2),
+           ('SDR', sdram3),
            ('EINT', eint),
            ('PWM', pwm),
            ('GPIO', gpio),