add SDRAM clock output
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 2 Aug 2018 06:36:18 +0000 (07:36 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 2 Aug 2018 06:36:18 +0000 (07:36 +0100)
commit537d9ca6a39af4288e71c6e1c09b5104a203111b
tree57bcb5d580466e6693d4ed83771fbe7b2e0aa6f8
parent9a8190f066f0d66cfb39ded12493ad1a3c15b0b1
add SDRAM clock output
src/spec/i_class.py