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(parent: 28bfaba) | patch
add clock/reset to dummy platform, now sync domain exists
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 13 Nov 2021 19:45:57 +0000 (19:45 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 13 Nov 2021 19:45:57 +0000 (19:45 +0000)
commitb2975db7602be29830511c0e1f60a0bab037f945
tree8411df157bcad96fbd393bacaa676a670d9a2b24tree
parent28bfabafb750aa8e78ba07da61cc18a679c0cfeccommit | diff
add clock/reset to dummy platform, now sync domain exists
src/spec/testing_stage1.py diff | blob | history
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