From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 31 Jul 2018 07:20:30 +0000 (+0100)
Subject: fix cell bit widths if muxwidth = 1
X-Git-Url: https://git.libre-soc.org/?p=pinmux.git;a=commitdiff_plain;h=0e07cd1c35e098cac02d0278ed18f1e3d8090352;hp=0179d35e50fdba6b9a0c9bb3a77dfea16773d3e0

fix cell bit widths if muxwidth = 1
---

diff --git a/src/bsv/pinmux_generator.py b/src/bsv/pinmux_generator.py
index 79bfc0a..64ab885 100644
--- a/src/bsv/pinmux_generator.py
+++ b/src/bsv/pinmux_generator.py
@@ -202,7 +202,10 @@ def write_pmp(pmp, p, ifaces, iocells):
 
         for cell in p.muxed_cells:
             cellnum = cell[0]
-            cell_bit_width = bwid_template % p.get_muxwidth(cellnum)
+            bitwidth = p.get_muxbitwidth(cellnum)
+            if bitwidth == 0:
+                continue
+            cell_bit_width = bwid_template % bitwidth
             bsv_file.write(mux_interface.ifacefmt(cellnum, cell_bit_width))
 
         bsv_file.write("\n      endinterface\n")
@@ -275,8 +278,12 @@ def write_pmp(pmp, p, ifaces, iocells):
       // values for each mux assigned to a CELL
 ''')
         for cell in p.muxed_cells:
-            bsv_file.write(mux_interface.wirefmt(
-                cell[0], cell_bit_width))
+            cellnum = cell[0]
+            bitwidth = p.get_muxbitwidth(cellnum)
+            if bitwidth == 0:
+                continue
+            cell_bit_width = bwid_template % bitwidth
+            bsv_file.write(mux_interface.wirefmt(cellnum, cell_bit_width))
 
         iocells.wirefmt(bsv_file)
         ifaces.wirefmt(bsv_file)
@@ -298,9 +305,14 @@ def write_pmp(pmp, p, ifaces, iocells):
     interface mux_lines = interface MuxSelectionLines
 ''')
         for cell in p.muxed_cells:
+            cellnum = cell[0]
+            bitwidth = p.get_muxbitwidth(cellnum)
+            if bitwidth == 0:
+                continue
+            cell_bit_width = bwid_template % bitwidth
             bsv_file.write(
                 mux_interface.ifacedef(
-                    cell[0], cell_bit_width))
+                    cellnum, cell_bit_width))
         bsv_file.write("\n    endinterface;")
 
         bsv_file.write('''
diff --git a/src/parse.py b/src/parse.py
index 2dffeb3..b2e017a 100644
--- a/src/parse.py
+++ b/src/parse.py
@@ -122,6 +122,12 @@ class Parse(object):
     def get_muxwidth(self, cellnum):
         return self.muxed_cells_width[int(cellnum)]
 
+    def get_muxbitwidth(self, cellnum):
+        wid = self.get_muxwidth(cellnum)
+        if wid == 1:
+            return 0
+        return int(math.log(wid + 1, 2))
+
 
 if __name__ == '__main__':
     p = Parse()