From 2a86f1cc9d9cc210df305ea57a1e135b71df5753 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 10 Jun 2021 11:41:17 +0100 Subject: [PATCH] move PLL around slightly, VCO on east top --- src/spec/ls180.py | 5 +++-- src/spec/pinfunctions.py | 4 ++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/src/spec/ls180.py b/src/spec/ls180.py index ae6e648..ca3401e 100644 --- a/src/spec/ls180.py +++ b/src/spec/ls180.py @@ -87,7 +87,8 @@ def pinspec(): ps.vdd("I", ('E', 1), 0, 4, 1) ps.vdd("I", ('E', 2), 0, 4, 1) ps.vss("I", ('E', 3), 0, 4, 1) - ps.mspi("0", ('E', 4), 0) + ps.sys("", ('E', 4), 0, 5, 1) # analog VCO out in right top + ps.mspi("0", ('E', 5), 0) ps.gpio("", ('E', 9), 0, 0, 16) ps.eint("", ('E', 25), 0, 0, 3) ps.vss("I", ('E', 28), 0, 5, 1) @@ -102,7 +103,7 @@ def pinspec(): #ps.pwm("", ('N', 2), 0, 0, 2) comment out (litex problem 25mar2021) #ps.mspi("1", ('N', 7), 0) comment out (litex problem 25mar2021) #ps.sdmmc("0", ('N', 11), 0) # comment out (litex problem 25mar2021) - ps.sys("", ('N', 22), 0, 0, 6) # should be 6, to do all PLL pins + ps.sys("", ('N', 23), 0, 0, 5) # all but analog out in top right ps.vss("I", ('N', 28), 0, 7, 1) ps.vdd("I", ('N', 29), 0, 7, 1) ps.vss("I", ('N', 30), 0, 7, 1) diff --git a/src/spec/pinfunctions.py b/src/spec/pinfunctions.py index d93f82a..f5f61d7 100644 --- a/src/spec/pinfunctions.py +++ b/src/spec/pinfunctions.py @@ -285,11 +285,11 @@ def vdd(suffix, bank): return (RangePin("-"), [], None) def sys(suffix, bank): - return (['PLLCLK-', # incoming clock (to PLL) + return (['RST-', # reset line 'PLLSELA0-', 'PLLSELA1-', # PLL divider-selector + 'PLLCLK-', # incoming clock (to PLL) 'PLLTESTOUT+', # divided-output (for testing) 'PLLVCOUT+', # PLL VCO analog out (for testing) - 'RST-', # reset line ], [], 'CLK') # list functions by name here -- 2.30.2