From 303ac486f3db396cf6406e2d40932444a221b9e8 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 9 Jun 2021 16:07:02 +0100 Subject: [PATCH] rename sys_clk to sys_pllclk - conflict with litex --- src/spec/ls180.py | 2 +- src/spec/pinfunctions.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/spec/ls180.py b/src/spec/ls180.py index 737039d..d0393ea 100644 --- a/src/spec/ls180.py +++ b/src/spec/ls180.py @@ -206,7 +206,7 @@ def pinparse(psp, pinspec): # SYS elif name.startswith('sys'): domain = 'SYS' - if name == 'sys_clk': + if name == 'sys_pllclk': pad = ["p_"+name, name, name] elif name == 'sys_rst': #name = 'p_sys_rst_1' diff --git a/src/spec/pinfunctions.py b/src/spec/pinfunctions.py index d30bc03..d93f82a 100644 --- a/src/spec/pinfunctions.py +++ b/src/spec/pinfunctions.py @@ -285,7 +285,7 @@ def vdd(suffix, bank): return (RangePin("-"), [], None) def sys(suffix, bank): - return (['CLK-', # incoming clock (to PLL) + return (['PLLCLK-', # incoming clock (to PLL) 'PLLSELA0-', 'PLLSELA1-', # PLL divider-selector 'PLLTESTOUT+', # divided-output (for testing) 'PLLVCOUT+', # PLL VCO analog out (for testing) -- 2.30.2