From 77fb3298744942516f9ae3c5a6e5767e6e903923 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 13 Nov 2021 22:08:06 +0000 Subject: [PATCH] cleanup jtag.py for demo/test purposes --- src/spec/jtag.py | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/src/spec/jtag.py b/src/spec/jtag.py index 4b4f17a..f5feec5 100644 --- a/src/spec/jtag.py +++ b/src/spec/jtag.py @@ -6,9 +6,7 @@ using Staf Verhaegen (Chips4Makers) wishbone TAP from collections import OrderedDict from nmigen import (Module, Signal, Elaboratable, Cat) from nmigen.cli import rtlil -from c4m.nmigen.jtag.tap import IOType -from soc.debug.dmi import DMIInterface, DBGCore -from soc.debug.dmi2jtag import DMITAP +from c4m.nmigen.jtag.tap import IOType, TAP # map from pinmux to c4m jtag iotypes iotypes = {'-': IOType.In, @@ -61,11 +59,11 @@ class Pins: scan_idx += scanlens[iotype] # inc boundary reg scan offset -class JTAG(DMITAP, Pins): +class JTAG(TAP, Pins): # 32-bit data width here so that it matches with litex def __init__(self, pinset, domain, wb_data_wid=32): self.domain = domain - DMITAP.__init__(self, ir_width=4) + TAP.__init__(self, ir_width=4) Pins.__init__(self, pinset) # enumerate pin specs and create IOConn Records. @@ -135,7 +133,7 @@ class JTAG(DMITAP, Pins): if __name__ == '__main__': pinset = dummy_pinset() - dut = JTAG(pinset) + dut = JTAG(pinset, "sync") vl = rtlil.convert(dut) with open("test_jtag.il", "w") as f: -- 2.30.2