From eab82d3c99e0eb8033f1bfac0951ef02820a4cc7 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 13 Nov 2021 18:10:02 +0000
Subject: [PATCH] hooray got the output at least created in build/

---
 src/spec/testing_stage1.py | 26 ++++++++++++++++++++++++--
 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/src/spec/testing_stage1.py b/src/spec/testing_stage1.py
index c148598..abbaaf2 100644
--- a/src/spec/testing_stage1.py
+++ b/src/spec/testing_stage1.py
@@ -10,7 +10,7 @@ from nmigen import Elaboratable, Signal, Module
 # flexbus2, sdram1, sdram2, sdram3, vss, vdd, sys, eint, pwm, gpio)
 
 # File for stage 1 pinmux tested proposed by Luke,
-https://bugs.libre-soc.org/show_bug.cgi?id=50#c10
+# https://bugs.libre-soc.org/show_bug.cgi?id=50#c10
 
 
 def dummy_pinset():
@@ -81,6 +81,18 @@ class Blinker(Elaboratable):
         return m
 
 
+'''
+    _trellis_command_templates = [
+        r"""
+        {{invoke_tool("yosys")}}
+            {{quiet("-q")}}
+            {{get_override("yosys_opts")|options}}
+            -l {{name}}.rpt
+            {{name}}.ys
+        """,
+    ]
+'''
+
 # sigh, have to create a dummy platform for now.
 # TODO: investigate how the heck to get it to output ilang. or verilog.
 # or, anything, really.  but at least it doesn't barf
@@ -89,7 +101,17 @@ class DummyPlatform(TemplatedPlatform):
     connectors = []
     required_tools = []
     command_templates = ['/bin/true']
-    file_templates = TemplatedPlatform.build_script_templates
+    file_templates = {
+        **TemplatedPlatform.build_script_templates,
+        "{{name}}.il": r"""
+            # {{autogenerated}}
+            {{emit_rtlil()}}
+        """,
+        "{{name}}.debug.v": r"""
+            /* {{autogenerated}} */
+            {{emit_debug_verilog()}}
+        """,
+    }
     toolchain = None
     def __init__(self, resources):
         self.resources = resources
-- 
2.30.2