add GPIOs to south bank, move UART SPI SDR over by one (Mux1 column)
-rw-r--r-- 65 .gitignore
-rw-r--r-- 703 Makefile
-rw-r--r-- 2770 README.md
-rw-r--r-- 2127 README_old.md
-rw-r--r-- 460 bitbucket-pipelines.yml
drwxr-xr-x - docs
drwxr-xr-x - figure
drwxr-xr-x - src
drwxr-xr-x - test