X-Git-Url: https://git.libre-soc.org/?p=riscv-isa-sim.git;a=blobdiff_plain;f=README.md;h=018c7d3eadfe823050eb18862d14c6fa5aa0b9fb;hp=60c09223af023cae325732575a1379dc54a04d03;hb=HEAD;hpb=3a4e89322a8c8dac94185812a238f13789ab392f

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@@ -1,18 +1,15 @@
-RISC-V ISA Simulator
-======================
-
-Author  : Andrew Waterman, Yunsup Lee
-
-Date    : June 19, 2011
-
-Version : (under version control)
+Spike RISC-V ISA Simulator
+============================
 
 About
 -------------
 
-The RISC-V ISA Simulator implements a functional model of one or more
+Spike, the RISC-V ISA Simulator, implements a functional model of one or more
 RISC-V processors.
 
+Spike is named after the golden spike used to celebrate the completion of the
+US transcontinental railway.
+
 Build Steps
 ---------------