X-Git-Url: https://git.libre-soc.org/?p=riscv-isa-sim.git;a=blobdiff_plain;f=riscv%2Finsns%2Fc_srli.h;h=008ae6221e89985b2f3a0aef5c74e698137a9114;hp=f410fefda56322c0aa7d4d39caa2d5af3c75fbee;hb=be0555d585b332fd0496affe559c0a5a4e7e5644;hpb=7e35a2a62f7433060e2ab1c98b3afd8b8a69b829

diff --git a/riscv/insns/c_srli.h b/riscv/insns/c_srli.h
index f410fef..008ae62 100644
--- a/riscv/insns/c_srli.h
+++ b/riscv/insns/c_srli.h
@@ -1,3 +1,3 @@
 require_extension('C');
-require(insn.rvc_zimm() < xlen);
+require(insn.rvc_zimm() < xlen && insn.rvc_zimm() > 0);
 WRITE_RVC_RS1S(sext_xlen(zext_xlen(RVC_RS1S) >> insn.rvc_zimm()));