X-Git-Url: https://git.libre-soc.org/?p=riscv-isa-sim.git;a=blobdiff_plain;f=riscv%2Fmmu.h;h=a3f06c60e9d920ea81f78ee7c284ea4e46085fcf;hp=f0bc19d1f546b47a999e63b61d46654da97d86a8;hb=2dbcb01ca1c026b867cf673203646d213f6e6b5c;hpb=4856220f05094a870e9544523428b85ec597fd42

diff --git a/riscv/mmu.h b/riscv/mmu.h
index f0bc19d..a3f06c6 100644
--- a/riscv/mmu.h
+++ b/riscv/mmu.h
@@ -239,6 +239,24 @@ public:
 
   void register_memtracer(memtracer_t*);
 
+  int is_dirty_enabled()
+  {
+#ifdef RISCV_ENABLE_DIRTY
+    return 1;
+#else
+    return 0;
+#endif
+  }
+
+  int is_misaligned_enabled()
+  {
+#ifdef RISCV_ENABLE_MISALIGNED
+    return 1;
+#else
+    return 0;
+#endif
+  }
+
 private:
   simif_t* sim;
   processor_t* proc;