X-Git-Url: https://git.libre-soc.org/?p=riscv-isa-sim.git;a=blobdiff_plain;f=riscv%2Fprocessor.cc;h=2dd27496775c45b305ac8135f2f0d8e03bc155f4;hp=f177090c649f5beb5d843749b2bd57c2b70ab39a;hb=f5bdc2e34299e3721c9319ba92dc72149f6af8a2;hpb=f87cdfec1dd79afdabccc848e730d780589b8a65

diff --git a/riscv/processor.cc b/riscv/processor.cc
index f177090..2dd2749 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -112,10 +112,6 @@ void processor_t::parse_isa_string(const char* str)
   if (supports_extension('Q') && max_xlen < 64)
     bad_isa_string(str);
 
-  // advertise support for supervisor and user modes
-  isa |= 1L << ('s' - 'a');
-  isa |= 1L << ('u' - 'a');
-
   max_isa = isa;
 }