X-Git-Url: https://git.libre-soc.org/?p=riscv-isa-sim.git;a=blobdiff_plain;f=riscv%2Fprocessor.cc;h=7a5df901b315c7a5b1642c45415520cdcb659ef3;hp=5a57c285c9bcada230568c2bc76991987c8a9fd3;hb=0020b3b924417412200b4ce7eb423b4213443b02;hpb=b4997aa4be6ab17b7a838b53e1ddea32726dad66

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 5a57c28..7a5df90 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -155,7 +155,8 @@ void processor_t::reset()
   if (ext)
     ext->reset(); // reset the extension
 
-  sim->proc_reset(id);
+  if (sim)
+    sim->proc_reset(id);
 }
 
 // Count number of contiguous 0 bits starting from the LSB.