X-Git-Url: https://git.libre-soc.org/?p=riscv-isa-sim.git;a=blobdiff_plain;f=riscv%2Friscv.mk.in;h=80755e711c181794e3ea9cb96ea40443d06e1d2b;hp=60c440368d133ce4f524078bb6815856ca378059;hb=d6fcfdebf6a893bf37670fd67203d18653df4a0e;hpb=19efe7d1121ab0e1a3014a1554e7340fa958c13f

diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index 60c4403..80755e7 100644
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -15,6 +15,7 @@ riscv_hdrs = \
 	mmu.h \
 	processor.h \
 	sim.h \
+	simif.h \
 	trap.h \
 	encoding.h \
 	cachesim.h \