X-Git-Url: https://git.libre-soc.org/?p=riscv-isa-sim.git;a=blobdiff_plain;f=riscv%2Fsim.cc;h=0e38c53fa96444a263f1560cbf631e21edc45497;hp=009bb98845d3d9723132abe9a4e839169ae107cf;hb=aa8cbb1ccd3856fd5e0437b0e24cfd7a3b794b8e;hpb=0329b0741a698f102d64be4f0538427978bacb83

diff --git a/riscv/sim.cc b/riscv/sim.cc
index 009bb98..0e38c53 100644
--- a/riscv/sim.cc
+++ b/riscv/sim.cc
@@ -27,10 +27,11 @@ sim_t::sim_t(const char* isa, size_t nprocs, bool halted, reg_t start_pc,
              std::vector<std::pair<reg_t, mem_t*>> mems,
              const std::vector<std::string>& args,
              std::vector<int> const hartids, unsigned progsize,
-             unsigned max_bus_master_bits)
+             unsigned max_bus_master_bits, bool require_authentication)
   : htif_t(args), mems(mems), procs(std::max(nprocs, size_t(1))),
     start_pc(start_pc), current_step(0), current_proc(0), debug(false),
-    remote_bitbang(NULL), debug_module(this, progsize, max_bus_master_bits)
+    remote_bitbang(NULL),
+    debug_module(this, progsize, max_bus_master_bits, require_authentication)
 {
   signal(SIGINT, &handle_signal);