X-Git-Url: https://git.libre-soc.org/?p=riscv-isa-sim.git;a=blobdiff_plain;f=riscv%2Fsim.h;h=97e9edecb8dc08d758a4c4c46bace1127dd670c6;hp=257de5ba85acc8fbbea5416e0d2efcb0e91953a4;hb=d6fcfdebf6a893bf37670fd67203d18653df4a0e;hpb=19efe7d1121ab0e1a3014a1554e7340fa958c13f

diff --git a/riscv/sim.h b/riscv/sim.h
index 257de5b..97e9ede 100644
--- a/riscv/sim.h
+++ b/riscv/sim.h
@@ -6,6 +6,7 @@
 #include "processor.h"
 #include "devices.h"
 #include "debug_module.h"
+#include "simif.h"
 #include <fesvr/htif.h>
 #include <fesvr/context.h>
 #include <vector>
@@ -15,19 +16,6 @@
 class mmu_t;
 class remote_bitbang_t;
 
-// this is the interface to the simulator used by the processors and memory
-class simif_t
-{
-public:
-  // should return NULL for MMIO addresses
-  virtual char* addr_to_mem(reg_t addr) = 0;
-  // used for MMIO addresses
-  virtual bool mmio_load(reg_t addr, size_t len, uint8_t* bytes) = 0;
-  virtual bool mmio_store(reg_t addr, size_t len, const uint8_t* bytes) = 0;
-  // Callback for processors to let the simulation know they were reset.
-  virtual void proc_reset(unsigned id) = 0;
-};
-
 // this class encapsulates the processors and memory in a RISC-V machine.
 class sim_t : public htif_t, public simif_t
 {