X-Git-Url: https://git.libre-soc.org/?p=riscv-isa-sim.git;a=blobdiff_plain;f=riscv%2Fsim.h;h=9a0a10b2569ba4a6aa8190fb5a540108f5a85a72;hp=6c6e4350702d62b240a42730a20f0b3efbd8f901;hb=9d1e10a36e771bf8cfbf515e07e856e021c1007a;hpb=aa8cbb1ccd3856fd5e0437b0e24cfd7a3b794b8e

diff --git a/riscv/sim.h b/riscv/sim.h
index 6c6e435..9a0a10b 100644
--- a/riscv/sim.h
+++ b/riscv/sim.h
@@ -15,8 +15,19 @@
 class mmu_t;
 class remote_bitbang_t;
 
+// this is the interface to the simulator used by the processors and memory
+class simif_t
+{
+public:
+  // should return NULL for MMIO addresses
+  virtual char* addr_to_mem(reg_t addr) = 0;
+  // used for MMIO addresses
+  virtual bool mmio_load(reg_t addr, size_t len, uint8_t* bytes) = 0;
+  virtual bool mmio_store(reg_t addr, size_t len, const uint8_t* bytes) = 0;
+};
+
 // this class encapsulates the processors and memory in a RISC-V machine.
-class sim_t : public htif_t
+class sim_t : public htif_t, public simif_t
 {
 public:
   sim_t(const char* isa, size_t _nprocs,  bool halted, reg_t start_pc,