projects / riscv-isa-sim.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 58aa702) | patch
Narrow the interface used by the processors and memory to the top-level simulator...
authorPrashanth Mundkur <prashanth.mundkur@gmail.com>
Tue, 20 Feb 2018 23:16:53 +0000 (15:16 -0800)
committerAndrew Waterman <aswaterman@gmail.com>
Tue, 6 Mar 2018 18:07:03 +0000 (12:07 -0600)
commit4a97a05a6e806f7abcb6cd30685093aa5b9331a9
tree8454d198cbb618ab3e120871f48b7c9c0503e06btree
parent58aa702359ec56f0b26a3f10a2617a58c9818451commit | diff
Narrow the interface used by the processors and memory to the top-level simulator/htif.
This allows the implementation of an alternative top-level simulator class.
riscv/execute.cc diff | blob | history
riscv/interactive.cc diff | blob | history
riscv/mmu.cc diff | blob | history
riscv/mmu.h diff | blob | history
riscv/processor.cc diff | blob | history
riscv/processor.h diff | blob | history
riscv/sim.cc diff | blob | history
riscv/sim.h diff | blob | history
Simple-V augmented version of spike