From: Tim Newsome <tim@sifive.com>
Date: Mon, 19 Mar 2018 20:10:06 +0000 (-0700)
Subject: Fix spike-dasm. (#184)
X-Git-Url: https://git.libre-soc.org/?p=riscv-isa-sim.git;a=commitdiff_plain;h=0020b3b924417412200b4ce7eb423b4213443b02

Fix spike-dasm. (#184)

It had been broken by 90bafe660b323250338fd564bb9ab4316576d59b.
---

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 5a57c28..7a5df90 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -155,7 +155,8 @@ void processor_t::reset()
   if (ext)
     ext->reset(); // reset the extension
 
-  sim->proc_reset(id);
+  if (sim)
+    sim->proc_reset(id);
 }
 
 // Count number of contiguous 0 bits starting from the LSB.